參數(shù)資料
型號(hào): HMS97C8032
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A
中文描述: 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, MQFP-80
文件頁(yè)數(shù): 27/86頁(yè)
文件大?。?/td> 1508K
代理商: HMS97C8032
HMS91C7134
November.2001 ver1.0
27
9.3 Interrupt Priority structure
Each interrupt source can be assigned one of two priority levels.
Interrupt priority levels are defined by the interrupt priority spe-
cial function register IP and IPA.
“0” - low priority
“1” - high priority
A low priority interrupt may be interrupted by a high priority in-
terrupt level interrupt. A high priority interrupt routine cannot be
interrupted by any other interrupt source. If two interrupts of dif-
ferent priority occur simultaneously, the high priority level re-
quest is serviced. If requests of the same priority are received
simultaneously, an internal polling sequence determines which
request is serviced. Thus, within each priority level, there is a sec-
ond priority structure determined by the polling sequence. This
second priority structure is shown in Table 9.5.
Table 9-5 Priority levels
Note
The “Priority within level” structure is only used to resolve
simultaneous requests of the same priority level.
The MD interrupt needs a higher priority then ALL the oth-
er interrupts. This is to avoid that a mode change will not be
serviced in time and that the setting of the S-curve is not up-
dated in time. When the S-curve settings are not updated in
time (after a mode change) the monitor may be damaged.
Table 9-6 Interrupt Priority Register(IP: 0B8H) RESET VALUE: x0000000B
Table 9-7 Description of the IP bits
SOURCE
INT0
PRIORITY WITHIN LEVEL
MD
Timer0
I2C
INT1
DDC
Timer1
VSYNC
Timer2
1(highest)
9(lowest)
7
6
5
4
3
2
2
0
-
PVSYNC
PT2
PS
PT1
PX1
PT0
PX0
BIT
7
SYMBOL
-
FUNCTION
Reserved
Vsync interrupt priority level
Timer2 interrupt priority level
Not used
Timer1 interrupt priority level
External interrupt (INT1) priority level
Timer0 interrupt priority level
External interrupt (INT0) priority level
6
PVSYNC
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
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