參數(shù)資料
型號： HMS97C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A
中文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁數(shù)： 43/86頁
文件大?。?/td> 1508K
代理商： HMS97C8032
HMS91C7134
November.2001 ver1.0
43
16.1 The Special Function register for DDC Interface.
Eight SFR : S1CON, S1STA, S1DAT, S1ADR, RAMBUF, DDCCON, DDCADR, DDCDAT.
S1CON, S1STA, S1DAT, S1ADR are just the copies of the corresponding registers in general I2C-bus interface.
Table 16-1 DDC mode status and DDC1 control register (DDCCON : 0D7H) RESET VALUE:x00x0000B
Table 16-2 Description of the DDCCON bits
7
6
5
4
3
2
2
0
-
EX_DAT
SWENB
-
DDCINT
DDC1EN
SWHINT
M0
BIT
SYMBOL
FUNCTION
7
-
Reserved
6
EX_DAT
(R/W)
This bit defines the size of the EDID data. It is related to the function of the post increment of the
address pointer, DDCADR. When the upper limit is reached, the DDCADR will wrap around to
00H.
If EX_DAT is
1: The data size is 256 byte.
0: The data size is 128 byte(The addressing range for the EDID data buffer is mapped from 0 to
127 ; the rest, 128 to 255 , can still be used by the system).
This bit indicates if the software/CPU is needed to take care of the operation of DDC1 protocol.
If SWENB is
5
SWENB
(R/W)
1 : In DDC1 protocol, CPU is interrupted during the period of the 9th transmitting bit so that the
S/W service routine can update the hold register of transmitter by moving new data from appro-
priate area(it is not necessary to be the RAM buffer which is pointed by DDCADR) to the register
DDCDAT. This transmitting must be done within 40us.
0 : The hold register of the transmitter will be automatically updated from the RAM buffer without
the intervention of CPU.
Reserved
4
-
3
DDC1INT
(R/W)
Interrupt Request Bit. This bit is only valid in DDC1 protocol while S/W handling is enabled. This
bit is set by H/W and should be cleared by S/W in interrupt service routine.
1 : Interrupt request is pending.
0 : No interrupt request
DDC1 enable control bit. If DDC1EN is
2
DDC1EN
(R/W)
1 : DDC1 is enabled.
0 : DDC1 is disabled ; The activity on VSYNC is ignored.
Interrupt Request Bit. This bit is set by H/W when DDC interface switches from DDC1 to DDC2
(i.e. The voltage transient from high to low is observed on SCL1 pin). This bit should be cleared
by S/W in interrupt service routine.
1
SWHINT
(R/W)
1 : Interrupt request is pending.
0 : No interrupt request
DDC mode indication bit. This bit will be set by H/W when the voltage transient from high to low
is observed on SCL1 pin. Once mode changes into DDC2 mode, the mode is reserved until pow-
er is off.
0
M0
(R/W)
0: DDC1 is set.
1: DDC2 is set.
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