參數(shù)資料
型號(hào)： HMS91C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁(yè)數(shù)： 52/86頁(yè)
文件大?。?/td> 1508K
代理商： HMS91C7134
HMS91C7134
52
November.2001 ver1.0
17.1 The Special Function register for I
2
C Interface.
Serial Control Register(SXCON; S1CON, S2CON)
Table 17-1 Serial control register(SxCON; S1CON : 0D8H , S2CON : 0DCH)
Table 17-2 Description of the SxCON bits
Table 17-3 Selection of the serial clock frequency SCL in Master mode of operation.
7
6
5
4
3
2
1
0
CR2
ENI1
STA
STO
ADDR
AA
CR1
CR0
BIT
7
SYMBOL
CR2
FUNCTION
This bit along with bits CR1and CR0 determines the serial clock frequency when
SIO is in the Master mode.
6
ENI1
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the
high impedance state.
5
STA
START flag. When this bit is set, the SIO H/W checks the status of the I2C-bus
and generates a START condition if the bus free. If the bus is busy, the SIO will
generate a repeated START condition when this bit is set.
4
STO
STOP flag. With this bit set while in Master mode a STOP condition is
generated.
When a STOP condition is detected on the I2C-bus, the SIO hardware clears the
STO flag.
3
ADDR
This bit is set when address byte was received. Must be cleared by software.
2
AA
Acknowledge enable signal. If this bit is set, an acknowledge(low level to SDA)is
returned during the acknowledge clock pulse on the SCL line when :
Own slave address is received
A data byte is received while the device is programmed to be a Master Receiver
A data byte is received while the device is a selected Slave Receiver. When this
bit is reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
0
CR0
These two bits along with the CR2 bit determine the serial clock frequency when
SIO is in the Master mode.
1
CR1
CR2
CR1
f
osc
DIVISOR
BIT RATE (kHz) at f
osc
0
0
16
250
375
-
8MHz
12MHz
16MHz
CR0
0
0
0
14
285.71
428.57
-
1
0
1
40
100
150
-
0
0
1
60
66.67
100
-
1
1
0
120
33.33
50
-
0
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