參數(shù)資料
型號： HMS91C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁數(shù)： 49/86頁
文件大?。?/td> 1508K
代理商： HMS91C7134
HMS91C7134
November.2001 ver1.0
49
Example Program; DDC Interface
Initial & Interrupt part
Initial:
mov DDCCON,#01h
mov DDCADR,#0
mov DDCCON,#00100100b
mov S1CON,#47h
mov S1ADR0, #0A1h
mov S1ADR1, #41h
; SWENB(0)
;
; 128(6),DDC1_Int(5),DDC1_enable(1)
; 100kHz(011),ENI1(1),ACK_enable(1)
; DDC2B Slave address
; Factory Alignment Host
;=================================================================
; DDC Interface
; 1. ISR
S1STA
S1DAT
; 2. ISR
S1CON
Refresh
; 3. Slaver Receive Address match
!
"
S1DAT
; Dummy Data
Writing
$
.
%
Slave Receive
;======================================================.
; task
: DDC interrupt Service
; input
: Control & Status Peripheral register
;=================================================================
DDC_Header:
db
00,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,00
DDC_Isr:
push
PSW
push
DPH
push
DPL
push
ACC
push
00
push
01
mov
A, DDCCON
anl
A, #00001000b
jz
DDC2_svc
;===================================;
DDC1_mode:
mov
A, mIICFlag
anl
A,#00000011b
cjne
A, #03h, DDC1Enable
mov
A, #0FFh
mov
DDCDAT, A
ljmp
DDC_Int_end
.
.
#
S1STA
&'
;
;
;
;
;
;
;
; (1) DDC1INT request(bit3=1)
;
;bUserSoftDDC(1), bDDC1Enable(0)
;
;
;
;
DDC1Enable:
mov
mov
mov
cjne
mov
A, mDDCData
DDCDAT, A
A, mDDCAddress
A, #80h, DDC1_Svc
DDCCON, #01h
;
;
;
;
; DDC1 Disable,DDC2 Mode
DDC1_Svc:
clr
subb
jnc
mov
mov
movc
sjmp
C
A, #8
NormalDDC1
DPTR, #DDC_Header
A, R0
A, @A+DPTR
DDC1_Save
;
;
;
;
;
;
;
NormalDDC1:
mov
add
mov
movx
DDC1_Save:
mov
inc
ljmp
;=================DDC_Int_end
DDC2_svc:
mov
A, DDCCON
anl
A, #00000010b
jz
DDC_I2C_svc
mov
mDDCAddress, #00h
mov
DDCCON, #00000001b ;
DDC_I2C_svc:
mov
A, S1STA
mov
mI2C_status,A
anl
A, #11000110b
jnz
DDC_Abnormal
mov
A, S1CON
anl
A, #00001000b
jnz
ADDR_Match
ljmp
DDC2B_svc
Addr_Match:
mov
DDCCON, #01h
setb
bI2C_Dir
mov
A, S1DAT
anl
A, #0FEh
cjne
A, #60h, DDC2B_mode ; 60h = Factory Host
A, #EDID_DATA
A, R0
R0, A
A, @R0
;
; data post
;
;
DDCDAT, A
mDDCAddress
;
;
;
;
; (2) SWHINT (SCLLow bit1=1) SCL activity
;
; (3) i2C abnormal by G-call,Stop, Arbitration and no Acknowledge
;
; 1 1 0 0 0 1 1 0
; GC,STOP,INTR,TX_MODE,BUSY,BLOST,/ACK_REP,SLV
;
; (4) Host address matched
;
; (5) 1 byte data access by DDC2B format
; DDC1 Disable,DDC2 Mode
; TX
;
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