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| 型號： | HMS91C7134 |
| 英文描述： | [Monitor] |
| 中文描述： | [顯示器] |
| 文件頁數(shù)： | 31/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS91C7134 |
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HMS91C7134
November.2001 ver1.0
31
Table 10-3 External Pin Status During Idle and Power-down modes
10.2 Idle mode
The instruction that sets PCON.0 is the last instruction executed
in the normal operating mode before idle mode is activated. Once
in the idle mode, the CPU status is preserved in its entirety : Stack
pointer, Program counter, Program status word, Accumulator,
RAM and All other registers maintain their data during idle
mode.
There are three ways to terminate the idle mode.
Activation of any enabled interrupt X0, T0, X1, T1 etc. will
cause PCON.0 to be cleared by hardware terminating Idle
mode. The interrupt is serviced, and following return from
interrupt instruction RETI, the next instruction to be execut-
ed will be the one which follows the instruction that wrote a
logic 1 to PCON.0.
External hardware reset : the hardware reset is required
to be active for two machine cycle to complete the reset op-
eration.
Internal watchdog reset : the microcontroller restarts after
3 machine cycles in all cases.
10.3 Power-down mode
The instruction that sets PCON.1 is the last executed prior to go-
ing into the Power-down mode. Once in Power-down mode, the
oscillator is stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The power-down mode can be terminated by an external RESET
in the same way as in the 80C51 (but SFRs are cleared due to RE-
SET).
MODE
Idle
Power-down
MEMORY
Intenal
Intenal
PORT0-3
Data
Data
SYNC
on
High
PWM
High
High
I2C
High-Z
High-Z
DDC
on
High-Z
-
-
-
-
-
-
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| HMS97C7132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:[Monitor] |
| HMS97C7134 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:[Monitor] |
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