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| 型號(hào)： | HMS91C7134 |
| 英文描述： | [Monitor] |
| 中文描述： | [顯示器] |
| 文件頁數(shù)： | 29/86頁 |
| 文件大小： | 1508K |
| 代理商： | HMS91C7134 |
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HMS91C7134
November.2001 ver1.0
29
9.4 How Interrupt are handled
The interrupt flags are sampled at S5P2 of every machine cycle.
The samples are polled during following machine cycle. If one of
the flags was in a set condition at S5P2 of the preceding cycle, the
polling cycle will find it and the interrupt system will generate an
LCALL to the appropriate service routine, provided this H/W
generated LCALL is not blocked by any of the following condi-
tions :
An interrupt of equal priority or higher priority level is al-
ready in progress.
The current machine cycle is not the final cycle in the ex-
ecution of the instruction in progress.
The instruction in progress is RETI or any access to the
interrupt priority or interrupt enable registers.
The polling cycle is repeated with each machine cycle, and the
values polled are the values that were present at S5P2 of the pre-
vious machine cycle. Note that if an interrupt flag is active but be-
ing responded to for one of the above mentioned conditions, if the
flag is still inactive when the blocking condition is removed, the
denied interrupt will not be serviced. In other words, the fact that
bered. Every polling cycle is new.
The processor acknowledges an interrupt request by executing a
hardware generated LCALL to the appropriate service routine.
The hardware generated LCALL pushes the contents of the Pro-
gram Counter on to the stack (but it does not save the PSW) and
reloads the PC with an address that depends on the source of the
interrupt being vectored to as shown in Table 9-10.
Execution proceeds from that location until the RETI instruction
is encountered. The RETI instruction informs the processor that
the interrupt routine is no longer in progress, then pops the top
two bytes from the stack and reloads the Program Counter. Exe-
cution of the interrupted program continues from where it left off.
Note that a simple RET instruction would also return execution
to the interrupted program, but it would have left the interrupt
control system thinking an interrupt was still in progress, making
future interrupts impossible.
Table 9-10 Vector addresses
SOURCE
INT0
VECTOR ADDRESS
0003H
MD
004BH
000BH
Timer0
I2C
INT1
0043H
0013H
DDC
Timer1
003BH
001BH
VSYNC
Timer2
0033H
002BH
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| HMS97C7132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:[Monitor] |
| HMS97C7134 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:[Monitor] |
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