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| 型號： | HMS91C7134 |
| 英文描述： | [Monitor] |
| 中文描述： | [顯示器] |
| 文件頁數(shù)： | 40/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS91C7134 |
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HMS91C7134
40
November.2001 ver1.0
Table 15-3 Timer Control register(TCON) RESET VALUE:00000000B
Table 15-4 Description of the TCON bits
15.2 TIMER2
Timer2 is a 16-bit auto-reload timer. The 16-bit capture mode,
baud rate generation mode and an event counter function that the
Timer/Counter2 in 80C52 core has are eliminated. Since the
clock of this timer comes from the system oscillator, Timer2 can
be used to count a time period more accurately comparing with
Timer0 and Timer1, but the longest period is limited as 65536 x
(tOSC/2).
The interval between interrupt =
65536 x (2 x tOSC) - (RC2H x 256 + RC2L) x (2 x tOSC)
The maximum interrupt period =
65536 x (2 x tOSC)
Table 15-5 Timer2 control register (T2CON : 0C8H) RESET VALUE:0xxxx0xxB
Table 15-6 Description of the TCON bits
7
6
5
4
3
2
2
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
BIT
SYMBOL
FUNCTION
7
TF1
Timer1 overflow flag. Set by hardware on Timer oveflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer1 run control bit. Set/cleared by software to turn Timer on/off .
6
TR1
5
TF0
Timer0 overflow flag. Set by hardware on Timer oveflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer0 run control bit. Set/cleared by software to turn Timer on/off .
4
TR0
3
IE1
Interrupt1 edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
Interrupt1 type control bit. Set/cleared by software to specified falling
2
IT1
edge/low level triggered external interrupts.
I
nterrupt0 edge flag. Set by hardware when external interrupt edge detected.
1
IE0
Cleared when interrupt processed.
Interrupt0 type control bit. Set/cleared by software to specified falling
0
IT0
edge/low level triggered external interrupts.
7
6
5
4
3
2
2
0
TF2
-
-
-
-
TR2
-
-
BIT
SYMBOL
FUNCTION
7
TF2
Timer2 overflow flag. Set by hardware on Timer overflow.
Must be cleared by software.
Reserved
6 to 3
-
2
TR2
Timer2 run control bit. set/cleared by software to turn Timer on/off.
1 to 0
TR0
Reserved
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