參數(shù)資料
型號(hào)： HMS91C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁(yè)數(shù)： 51/86頁(yè)
文件大小： 1508K
代理商： HMS91C7134
HMS91C7134
November.2001 ver1.0
51
17. I2C INTERFACE
In the Monitor MCU are two I2C interfaces implemented.
The first one is used by the DDC protocols.
The second one is dedicated for internal connection. With this one it s possible to control the video, deflection, conver-
gence and some other functions of the monitor.
The serial port supports the twin line I2C-bus, consists of a data line(SDAx) and a clock line(SCLx).
SDA1, SCL1 : the serial port line for DDC Protocol
SDA2, SCL2 : the serial port line for Internal Connection
In both I2C interfaces, these lines also function as I/O port lines as follows.
SDA1 / P1.1, SCL1 / P1.0, SDA2 / P1.7, SCL2 / P1.6
The system is unique because data transport, clock generation, address recognition and bus control arbitration are
all controlled by hardware.
The I2C serial I/O has complete autonomy in byte handling and operates in 4 modes.
Master transmitter
Master receiver
Slave transmitter
Slave receiver
These functions are controlled by the SFRs.
SxCON : the control of byte handling and the operation of 4 mode.
SxSTA : the contents of its register may also be used as a vector to various service routines.
SxDAT : data shift register.
SxADR : slave address register. Slave address recognition is performed by On-Chip H/W.
Figure 17-1 The block diagram of the I2C-bus serial I/O.
Slave Address
Shift Register
Arbitration + Sync. Logic
Bus Clock Generation
Control Register
Status Register
I
SDAx
SCLx
-
7
0
0
0
0
7
7
7
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