參數(shù)資料
型號(hào)： HMS91C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁數(shù)： 25/86頁
文件大小： 1508K
代理商： HMS91C7134
HMS91C7134
November.2001 ver1.0
25
Timer0 and Timer1 interrupt:
Timer0 and Timer1 interrupts are generated by TF0 and TF1
which are set by an overflow of their respective Timer/Counter
registers(except for Timer0 in mode3).
These flags are cleared by the internal hardware.
Timer2 interrupt:
Timer2 interrupt is generated by TF2 which is set by an overflow
of Timer2.
This flag has to be cleared by the software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or
cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
Figure 9-1 Interrupt system
INT0
MD
Timer0
I2C
INT1
DDC
Timer1
VSYNC
Not
used
Timer2
High
Low
I
Interrupt
Sources
IE / IEA
IP / IPA
Priority
Global
Enable
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