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參數(shù)資料
| 型號(hào)： | HMC700LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1064-6 |
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
Figure 15. Serial Port Timing Diagram - Write Serial Port WRITE Operation
Serial Port READ Operation
a typical rEaD cycle is shown in Figure 16.
a. the Master (host) asserts both SEn (Serial Port Enable) and SDi to indicate a rEaD cycle, followed
by a rising edge ScK. note: the Lock Detect function is multiplexed onto the LD_SDo pin. it is
suggested that lock detect (LD) only be considered valid when SEn is low. in fact LD will not toggle
until the first active data bit toggles on LD_SDo, and will be restored immediately after the trailing
edge of the LSB of serial data out as shown in Figure 15.
b. the slave (synthesizer) reads SDi on the 1st rising edge of ScK after SEn. SDi high initiates the
rEaD cycle (rD).
c. Host places the six address bits on the next six falling edges of ScK, MSB first.
d. Slave registers the address bits on the next six rising edges of ScK (2-7).
e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDo on the next 24
rising edges of ScK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of ScK (8-31).
g. Slave restores Lock Detect on the 32nd rising edge of ScK.
h. SEn is de-asserted on the 32nd falling edge of ScK.
i. the 32nd falling edge of ScK completes the rEaD cycle.
Figure 16. Serial Port Timing Diagram - READ Serial Port Operation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HMC700LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN 制造商:Hittite Microwave Corp 功能描述:HMC700 Series 8 GHz 16-Bit Prescaler Fractional-N PLL - 4x4 mm QFN-24 |
| HMC701LP6C | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6C_10 | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
| HMC702LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
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