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參數(shù)資料
| 型號(hào)： | HMC700LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁(yè)數(shù)： | 8/26頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1064-6 |
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
it is also possible to leave various blocks on when in Power Down (see table 8), including:
a. Digital clocks
b. internal bias reference sources
c. PFD block
d. charge Pump Block
e. reference Path buffer
f. Vco Path buffer
g. Digital i/o test pads
Chip Identification
the version of the synthesizer is described in Table 6. Version information may be read from the synthesizer by
reading the content of chip_ID in reg 00h.
SERIAL PORT
typical serial port operation can be run with ScK at speeds up to 50MHz.
Serial Port WRITE Operation
Table 4. Timing Characteristics
Parameter
conditions
Min
typ
Max
Units
t1
SEn to ScK Setup time
8
nsec
t2
SDi to ScK Setup time
5
nsec
t3
SDi to ScK Setup time
5
nsec
tsck
ScK period
20
nsec
t4
ScK High Duration
8
nsec
t5
ScK Low Duration
8
nsec
t6
SEn High Duration
640
nsec
t7
SEn Low Duration
20
nsec
a typical WritE cycle is shown in Figure 15.
a. the Master (host) both asserts SEn (Serial Port Enable) and clears SDi to indicate a WritE cycle,
followed by a rising edge of ScK.
b. the slave (synthesizer) reads SDi on the 1st rising edge of ScK after SEn. SDi low initiates the Write
cycle (/Wr).
c. Host places the six address bits on the next six falling edges of ScK, MSB first.
d. Slave registers the address bits in the next six rising edges of ScK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of ScK, MSB first .
f. Slave registers the data bits on the next 24 rising edges of ScK (8-31).
g. SEn is de-asserted on the 32nd falling edge of ScK.
h. the 32nd falling edge of ScK completes the cycle.
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| HMC700LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN 制造商:Hittite Microwave Corp 功能描述:HMC700 Series 8 GHz 16-Bit Prescaler Fractional-N PLL - 4x4 mm QFN-24 |
| HMC701LP6C | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6C_10 | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
| HMC702LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
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