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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
PFD Jitter and Lock Detect Background (Continued)
With this simplification the total integrated Vco phase noise, f2, in rads2 at the phase detector is given by
where
B is the 3 dB corner frequency of the closed loop PLL
n is the division ratio of the prescaler
Since the simple integral of (EQ 1) is just a product of constants, we can easily do the integral in the log domain. For
example if the Vco phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is 100 kHz,
and the division ratio is 100, then the integrated phase noise at the phase detector, in dB, is given by:
f 2
dB = 10log (f
2
(0) Bπ/N2) = -100 +50 +5 -40 = 85dBrads2
or equivalently, f = 10-85/20 = 56.2 urads = 3.22 milli-degrees rms.
While the phase noise reduces by a factor of 20logn after division to the reference, due to the increased period of the
PFD reference signal, the jitter is constant.
the rms jitter from the phase noise is then given by Tjpn = TPFDf /2π
in this example if the PFD reference was 50MHz, tPFD = 20nsec, and hence tjpn = 0.179 psec.
a normal 3 sigma peak-to-peak variation in the arrival time therefore would be ±3tjpn = ±0.759 psec.
if the synthesizer was in fractional mode, the fractional modulation of the Vco divider will dominate the jitter. the
exact standard deviation of the divided Vco signal will vary based upon the modulator type chosen, however a typical
modulator will vary by about ±3 division ratios, ±4 division ratios, worst case.
if, for example a nominal Vco at 5 GHz is divided by 100 to equal the PFD reference at 50 MHz, then the worst
case division ratios will vary by 100 ±4. Hence the peak variation in the arrival times caused by ∑ modulation of the
fractional synthesizer at the reference will be
if we note that the distribution of the delta sigma modulation is approximately Gaussian, we could approximate TjΔ∑pk
as a 3 sigma jitter, and hence we could estimate the rms jitter of the ∑ modulator as about 1/3 of TjΔ∑pk or about 266
psec in this example.
Hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the Vco would be
given by the rms sum, where
in this example the jitter contribution of the phase noise calculated previously would add only 0.18psec more jitter at
the reference, hence we see that the jitter at the phase detector is totally dominated by the fractional modulation.
Hence, we have to expect about ±800 psec of normal variation in the phase detector arrival times when in fractional
mode. in addition, lower Vco frequencies with high PFD reference frequencies will have much larger variations. For
example a 1GHz Vco operating at near the minimum nominal divider ratio of 36, would according to (EQ 2) exhibit
about ±4 nsec of peak variation at the phase detector, under normal operation.
(EQ 1)
(EQ 2)
(EQ 3)