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參數(shù)資料
| 型號： | HMC700LP4E |
| 廠商： | Hittite Microwave Corporation |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRACT-N PLL 16BIT 24QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 整數(shù) N/小數(shù) N 分頻 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V，5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 1127-1064-6 |
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
Charge Pump Gain
a simplified diagram of the charge pump is shown in Figure 14. charge pump up and down gains are set by
cp_UPcurrent_sel and cpDNcurrent_sel respectively (table 16). Each of the UP and Dn charge pumps consist of
two 500ua current sources and one 1000ua current source. the current gain of the pump in radians/amp is equal to
the gain setting of this register divided by 2π. For example if both cp_UPcurrent_sel and cpDNcurrent_sel are set to
’010’ the output current of each pump will be 1ma and the phase detector gain Kp = 1ma/2π radians, or 159ua/rad.
Charge Pump Gain Trim
Each of the UP and Dn pumps may be trimmed to more precise values to improve current source matching or to allow
finer control of pump gain. the pump trim controls are 4bits, binary weighted for UP and Dn, in cp_UPtrim_sel and
cp_DNtrim_sel respectively (table 16). LSB weight is 7a, maximum trim is 105a.
Charge Pump Phase Offset
ideally the phase detector operates with zero offset, that is, the divided reference signal and the divided Vco signal
arrive at the phase detector inputs at exactly the same time. in some modes of operation, such as fractional mode,
charge pump linearity and ultimately, phase noise, is better if the Vco and reference inputs are operated with a phase
offset. normally integer mode of operation is best with no phase offset. a phase offset is implemented by adding a
constant Dc leakage to one of the charge pumps. Dc leakage may be added to the UP or Dn pumps using chp_
UPoffset_sel or chp_DNoffset_sel. these are 3 bit registers with 55a LSB. Maximum offset is 385ua.
For best spectral performance in Fractional Mode the leakage current should be programmed to: required Leakage
current (ua) = (4E-9 + 4xtvco) x Fcomparison (Hz) x cP current (ua)
Charge Pump Operation Near the Rail
it should be noted that the charge pump is a non-ideal device. Phase locked operation with the tuning voltage very
near the positive charge pump supply voltage or very near ground will degrade the phase noise performance of the
synthesizer. Exactly how close to the supply limits that one should operate is a question of margin needed for the
application in question and user judgement. Figure 3. gives some idea of the typical performance near the supply
limits. it should be noted that if operation is necessary very near the supply limits, for example less than 500mV
from the supply limit, then it is recommended to operate with a Dc leakage that leaks in the direction of the supply.
For example, if the charge pump supply is 5.5V and locked operation is required with a Vco tune voltage of 5.2V,
then operating with UP leakage on the charge pump will improve operation in this region. Similarly if phase locked
operation is needed, with a Vco tune voltage of say 300mV, then operating with Dn leakage is recommended.
as an example, if the main pump gain was set at 1ma, an offset of 385ua would represent a phase offset of about
(385/1000)*360 = 138degrees. normally it is sufficient to offset the pump by just slightly larger than the delta sigma
excursions for best phase noise. Best spurious operation usually occurs with Dn offset with non-inverting loop filters
and UP offset with inverting loop filters.
Figure 14. Charge Pump Gain & Offset Control
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參數(shù)描述 |
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| HMC700LP4ETR | 制造商:Hittite Microwave Corp 功能描述:IC FRACT-N PLL 16BIT 24QFN 制造商:Hittite Microwave Corp 功能描述:HMC700 Series 8 GHz 16-Bit Prescaler Fractional-N PLL - 4x4 mm QFN-24 |
| HMC701LP6C | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6C_10 | 制造商:HITTITE 制造商全稱:Hittite Microwave Corporation 功能描述:8 GHz 16-BIT FRACTIONAL-N SYNTHESIZER |
| HMC701LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
| HMC702LP6CE | 制造商:Hittite Microwave Corp 功能描述:IC SYNTHESIZER W/SWEEPER 40-QFN |
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