參數(shù)資料
型號: HMC700LP4E
廠商: Hittite Microwave Corporation
文件頁數(shù): 25/26頁
文件大小: 0K
描述: IC FRACT-N PLL 16BIT 24QFN
標(biāo)準(zhǔn)包裝: 1
類型: 整數(shù) N/小數(shù) N 分頻
PLL:
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 8GHz
除法器/乘法器: 是/無
電源電壓: 3.3V,5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 1127-1064-6
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
RF Path ’N’ Divider
the main rF path divider is capable of average divide ratios between 216 -1 (65,535) and 36 in fractional mode, and
216 + 31 (65,567) to 32 in integer mode.
Charge Pump and Phase Frequency Detector
the Phase Frequency Detector or PFD has two inputs, one from the reference path divider and one from the rF path
divider. When in lock these two inputs are at the same average frequency and are fixed at a constant average phase
offset with respect to each other. We refer to the frequency of operation of the PFD as PFD. Most formula related to
step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the PFD, PFD. the PFD
compares the phase of the rF path signal with that of the reference path signal and controls the charge pump output
current as a linear function of the phase difference between the two signals. the output current varies linearly over a
full ±2π radians input phase difference.
PFD Test Functions
Phase detector registers are mainly used in test. pfd_phase_sel in table 18 reverses the polarity of the phase
detector, to allow for negative slope Vco or inverting op-amp in the loop filter.
pfd_up_en in table 18 allows masking of the PFD up output, which effectively prevents the charge pump
from pumping up.
pfd_dn_en in table 18 allows masking of the PFD down output, which effectively prevents the charge pump
from pumping down.
De-asserting both pfd_up_en and pfd_dn_en effectively tri-states the charge pump while leaving all other
functions operating internally.
PFD Jitter and Lock Detect Background
in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided
crystal signal, known as the PFD reference signal. Despite the fact that the device is in lock, the phase of the Vco
signal and the PFD reference signal vary in time due to the phase noise of the reference and Vco oscillators, the loop
bandwidth used and the presence of fractional modulation or not. the total integrated noise from the Vco normally
dominates the variations in the two arrival times at the phase detector in integer mode.
if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and
phase jitter when not in lock.
First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional
modes.
the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a
simple approximation if we assume that the locked Vco has a constant phase noise, Ф2 (0), at offsets less than
the loop 3 dB bandwidth and a 20 dB per decade rolloff at greater offsets. the simple locked Vco phase noise
approximation is shown in Figure 10.
Figure 10. Synthesizer Phase Noise & Jitter
Ф2 (0)
r2/Hz
0
B
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