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參數(shù)資料
| 型號(hào)： | HD74AC |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | HD74AC Series Common Information |
| 中文描述： | HD74AC系列通用信息 |
| 文件頁(yè)數(shù)： | 46/52頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | HD74AC |
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Design Considerations
45
0.1"
0.1"
0.1"
0.04"
0.04"
V
1/16" Glass Epoxy
a) 50
V
CC
Impedance
Gnd
V
1/16 Board
b) 100
V
CC
Impedance
Gnd
1/16 Board
V
c) 68
V
CC
Impedance
Gnd
1/16 Board
V
d) 100
V
CC
Impedance
Gnd
032
V
e) 2
V
Impedance
Figure 17 Power Distribution Impedances
3.9 V
78 mA
4 ns
Ground
Plane
Worst-Case Octal Drain = 8
×
78 mA = 0.624 Amp.
Buffer Output Sees Net 50
Load.
50
Load Line on I
-V
Characteristic
Shows Low-to-High Step of Approx. 3.9 V
0
0 V
I
OH
V
OUT
100
Buffer
Data Bus
1 of 8
100
Figure 18 Octal Buffer Driving a 100
Bus
Q = CV
I = C
V/
t
C = I
t/
V
t = 4
×
10
–9
I = 0.75 A
C
B
V
CC
Bus
Z
CC
Bypass Capacitors
Specify V
CC
Droop = 0.1 V max.
C =
Select C
B
≥
0.047
μ
F
= 25
×
10
–9
= 0.025
μ
F
0.1
0.624
×
4
×
10
–9
V
CC
Place one decoupling capacitor adjacent to each package driving any transmission line and distribute others
evenly thoughout the logic. One capacitor per three packages.
Figure 19 Formula for Calculating Decoupling Capacitors
In this example, if the V
CC
droop is to be kept below 0.1 V and the edge rate equals 4 ns, a 0.025
μ
F
capacitor is needed.
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| HD74AC00 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:Quad 2-Input NAND Gate |
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| HD74AC00P | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:Quad 2-Input NAND Gate |
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