參數(shù)資料
型號: HD74AC
廠商: Hitachi,Ltd.
英文描述: HD74AC Series Common Information
中文描述: HD74AC系列通用信息
文件頁數(shù): 36/52頁
文件大?。?/td> 220K
代理商: HD74AC
Design Considerations
35
2. Line Driving
With the available high-speed logic families, designers can reach new heights in system performance. Yet,
these faster devices require a closer look at transmission line effects.
Although all circuit conductors have transmission line properties, these characteristics become significant
when the edge rates of the drivers are equal to or less than three times the propagation delay of the line.
Significant transmission line properties may be exhibited in an example where devices have edge rates of 3
ns and lines of 8 inches or greater, assuming propagation delays of 1.7 ns/ft for an unloaded printed circuit
trace.
Of the many properties of transmission lines, two are of major interest to the system designer: Zoe, the
effective equivalent impedance of the line, and t
pde
, the effective propagation delay down the line. It should
be noted that the intrinsic values of line impedance and propagation delay, Z
O
and t
pd
, are geometry-
dependent. Once the intrinsic values are known, the effects of gate loading can be calculated. The loaded
values for Zoe and t
pde
can be calculated with:
Z
=
Z
C / C
t
1
oe
O
I
+
t
= t
1+ C / C
pde
pd
t
I
where C
I
= intrinsic line capacitance and Ct = additional capacitance due to gate loading.
The formulas indicate that the loading of lines decreases the effective impedance of the line and increases
the propagation delay. Lines that have a propagation delay greater than one third the rise time of the signal
driver should be evaluated for transmission line effects. When performing transmission line analysis on a
bus, only the longest, most heavily loaded and the shortest, least loaded lines need to be analyzed. All lines
in a bus should be terminated equally; if one line requires termination, all lines in the bus should be
terminated. This will ensure similar signals on all of the lines.
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