參數(shù)資料
型號: HD74AC
廠商: Hitachi,Ltd.
英文描述: HD74AC Series Common Information
中文描述: HD74AC系列通用信息
文件頁數(shù): 27/52頁
文件大?。?/td> 220K
代理商: HD74AC
Definition of Specifications
26
CONTROL
IN
CLOCK
t
PHL
t
PLH
Vmo
Vmi
Vmi
Vm
tw
t
rec
OUTPUT
Vmi = 50% V
CC
for HD74AC devices; 1.5 V for HD74ACT devices
Vmo = 50% V
CC
for HD74AC/HD74ACT devices
Figure 4 Propagation Delay, Pulse Width, and t
rec
Waveforms
3.5 Enable and Disable Times
Figures 5 and 6 show that the disable times are measured at the point where the output voltage has risen or
fallen by 10% from the voltage rail level (i.e., ground for t
LZ
or V
CC
for t
HZ
) . This change enhances the
repeatability of measurements, reduces test time, and gives the system designer more realistic delay times
to use in calculating minimum cycle times. Since the high-impedance state rising or falling waveform is
RC-controlled, the first 10% of change is more linear and is less susceptible to external influences. More
importantly, perhaps from the system designer’s point of view, a change in voltage of 10% is adequate to
ensure that a device output has turned off. Measuring to a larger change in voltage merely exaggerates the
apparent Disable time and thus penalizes system performance since the designer must use the Enable and
Disable times to device worst case timing signals to ensure that the output of one device is disabled befor
that of another device is enabled.
OUTPUT
CONTROL
DATA
OUT
Vmi
Vmo
–0.3 V
V
CC
90% V
CC
t
HZ
t
ZH
Vmi = 50% V
CC
for HD74AC devices; 1.5 V for HD74ACT devices
Vmo = 50% V
CC
for HD74AC/HD74ACT devices
Figure 5 3-State Output High Enable and Disable Times
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