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參數(shù)資料
| 型號： | HD74AC |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | HD74AC Series Common Information |
| 中文描述： | HD74AC系列通用信息 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大?。?/td> | 220K |
| 代理商： | HD74AC |
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Definition of Specifications
29
Table 6 AC Characteristics
Symbol
Term
Description
f
max
Maximum clock frequency
Maximum clock frequency that maintains the stable
changes in output logic level in the rated sequence
under the I/O condition allowing clock pulses to
change the output state
t
TLH
Rise (transient) time
Rated time from low level to high level of a
wavefrom during the defined transient period
changing from low level to high level
t
THL
Fall (transient) time
Rated time from high level to low level of a
wavefrom during the defined transient period
changing from high level to low level
t
PLH
Output rise propagation delay time
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the output changing from low level
to high level
t
PHL
Output fall propagation delay time
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the output changing from high level
to low level
t
HZ
3-state output disable time (high level)
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from
high level to the high-impendance state
t
LZ
3-state output disable time (low level)
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from low
level to the high-impendance state
t
ZH
3-state output enable time (high level)
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from the
high-impendance state to high level
t
ZL
3-state output enable time (low level)
Delay time between the rated voltage levels of an
I/O voltage waveform under a defined load
condition, with the 3-state output changing from the
high-impendance state to low level
t
w
Pulse width
Duration of time between the rated levels from a
leading edge to a trailing edge of a pulse waveform
t
h
Hold time
Time in which to hold data at the specified input
terminal after a change at another related input
terminal (e.g., clock input)
t
SU
Setup time
Time in which to set up and keep data at the
specified input terminal before a change at another
related input terminal (e.g., clock input)
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