參數(shù)資料
型號(hào): GS816136
廠商: GSI TECHNOLOGY
英文描述: 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
中文描述: 16Mb的流水線和流量,通過(guò)同步唑的SRAM(1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 4/32頁(yè)
文件大?。?/td> 584K
代理商: GS816136
Rev: 2.07 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
4/32
1999, Giga Semiconductor, Inc.
Preliminary
GS816118/36T-225/200/180/166/150/133
TQFP Pin Description
Pin Location
Symbol
Typ
e
I
Description
37, 36
A
0
, A
1
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92, 97
80
63, 62, 59, 58, 57, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
A
2
A
18
I
Address Inputs
A
19
I
Address Inputs (x18 versions)
DQ
A1
DQ
A8
DQ
B1
DQ
B8
DQ
C1
DQ
C8
DQ
D1
DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
DQ
A1
DQ
A9
DQ
B1
DQ
B9
I/O
Data Input and Output pins (x36 Version)
51, 80, 1, 30
I/O
Data Input and Output pins (x36 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7,
25, 28, 29, 30
16
66
87
93, 94
I/O
Data Input and Output pins (x18 Version)
NC
No Connect (x18 Version)
DP
QE
BW
B
A
, B
B
I
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
Byte Write
Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/’s; active low
(x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable
Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
O
I
I
95, 96
B
C
, B
D
I
95, 96
89
88
98
86
83
84, 85
NC
CK
GW
E
1
G
ADV
I
I
I
I
I
I
ADSP, ADSC
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GS816118 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
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