參數(shù)資料
型號(hào)： GS816136
廠商： GSI TECHNOLOGY
英文描述： 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
中文描述： 16Mb的流水線和流量，通過同步唑的SRAM（1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存）
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 584K
代理商： GS816136
Rev: 2.07 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
25/32
1999, Giga Semiconductor, Inc.
Preliminary
GS816118/36T-225/200/180/166/150/133
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS816118 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM)
GS8161E18BD-200I 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-200I 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18BGD-250I 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816136BD-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays
GS816136BD-150I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays
GS816136BD-150IV 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays
GS816136BD-150V 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays
GS816136BD-200 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 18MBIT 512KX36 6.5NS/3NS 165FBGA - Trays
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