參數(shù)資料
型號(hào)： GS1560A*
英文描述： Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply.
中文描述： 時(shí)鐘重計(jì)解串器的HD - SDI的。標(biāo)清SDI
文件頁(yè)數(shù)： 7/55頁(yè)
文件大?。?/td> 922K
GENNUM CORPORATION
27360 - 2
7 of 55
G
11
SD/HD
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The SD/HD signal will be LOW whenever the received serial digital signal
is 1.485Gb/s or 1.485/1.001Gb/s.
The SD/HD signal will be HIGH whenever the received serial digital signal
is 270Mb/s.
Slave Mode (MASTER/SLAVE = LOW)
When set LOW, the device will be configured for the reception of
1.485Gb/s or 1.485/1.001Gb/s signals only and will not lock to any other
serial digital signal.
When set HIGH, the device will be configured for the reception of 270Mb/s
signals only and will not lock to any other serial digital signal.
12
20bit/10bit
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the output data bus width in SMPTE or Data-Through
modes. This signal is ignored in DVB-ASI mode.
When set HIGH, the parallel output will be 20-bit demultiplexed data.
When set LOW, the parallel outputs will be 10-bit multiplexed data.
13
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
EDH CRC Error Correction (SD-only)
ANC Data Checksum Correction
Line-based CRC Error Correction (HD-only)
Line Number Error Correction (HD-only)
TRS Error Correction
Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accesible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
14
CD2
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI2 and DDI2
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
GS1561* Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply.
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GS15T48
GS15T5-5.2 DC-to-DC Voltage Converter
GS15T5-52 15W DC-DC CONVERTER FOR ECL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1560A_07 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer
GS1560A_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer
GS1560ACF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1560ACFE3 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80
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