參數(shù)資料
型號(hào)： GS1560A*
英文描述： Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply.
中文描述： 時(shí)鐘重計(jì)解串器的HD - SDI的。標(biāo)清SDI
文件頁(yè)數(shù)： 6/55頁(yè)
文件大小： 922K
GENNUM CORPORATION
27360 - 2
6 of 55
G
1.2 PIN DESCRIPTIONS
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
1
CP_VDD
-
Power
Power supply connection for the charge pump. Connect to +3.3V DC
analog.
2
PDBUFF_GND
-
Power
Ground connection for the phase detector and serial digital input buffers.
Connect to analog GND.
3
PD_VDD
-
Power
Power supply connection for the phase detector. Connect to +1.8V DC
analog.
4
BUFF_VDD
-
Power
Power supply connection for the serial digital input buffers. Connect to
+1.8V DC analog.
5
CD1
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI1 and DDI1
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
6,8
DDI1, DDI1
Analog
Input
Differential input pair for serial digital input 1.
7
TERM1
Analog
Input
Termination for serial digital input 1. AC couple to PDBUFF_GND.
9
DVB_ASI
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The DVB_ASI signal will be HIGH only when the device has locked to a
DVB-ASI compliant data stream. It will be LOW otherwise.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS =
LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word
alignment of received DVB-ASI data.
10
IP_SEL
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal,
and CD1 or CD2 as the carrier detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the serial digital input and
CD1 is selected as the carrier detect input signal.
When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect
input signal is selected.
相關(guān)PDF資料
PDF描述
GS1561* Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply.
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GS15T48
GS15T5-5.2 DC-to-DC Voltage Converter
GS15T5-52 15W DC-DC CONVERTER FOR ECL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1560A_07 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer
GS1560A_09 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer
GS1560ACF 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1560ACFE3 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80
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