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參數(shù)資料
| 型號： | GS1560A* |
| 英文描述： | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| 中文描述： | 時鐘重計解串器的HD - SDI的。標清SDI |
| 文件頁數(shù)： | 50/55頁 |
| 文件大?。?/td> | 922K |
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GENNUM CORPORATION
27360 - 2
50 of 55
G
3.12.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown
in Figure 18 and Figure 19 respectively. The maximum
SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the
data word may be presented to SDIN immediately following
the falling edge of the LSB of the command word. All SDIN
data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of
the data word will be available on SDOUT 12ns following
the falling edge of the LSB of the command word, and thus
may be read by the host on the very next rising edge of the
clock. The remaining bits are clocked out by the GS1560A
on the negative edges of SCLK.
Figure 18 GSPI Read Mode Timing
Figure 19 GSPI Write Mode Timing
3.12.3 Configuration and Status Registers
Table 17 summarizes the GS1560A's internal status and
configuration registers.
All of these registers are available to the host via the GSPI
and are all individually addressable.
Where status registers contain less than the full 16 bits of
information however, two or more registers may be
combined at a single logical address.
SDOUT
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
t
5
t
6
output data
hold time
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
TABLE 17 GS1560A INTERNAL REGISTERS
ADDRESS
REGISTER NAME
SEE SECTION
000h
IOPROC_DISABLE
Section 3.10.6
001h
ERROR_STATUS
Section 3.10.5
003h
EDH_FLAG
Section 3.10.7
004h
VIDEO_STANDARD
Section 3.10.4
005h - 009h
ANC_TYPE
Section 3.10.2.1
012h - 013h
VIDEO_FORMAT
Section 3.10.3
014h - 017h
RASTER_STRUCTURE
Section 3.10.4
018h - 025h
EDH_CALC_RANGES
Section 3.10.5.2
026h
ERROR_MASK
Section 3.10.5
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1560ACF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1560ACFE3 | 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80 |
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