參數(shù)資料
型號(hào)： GS1560A*
英文描述： Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply.
中文描述： 時(shí)鐘重計(jì)解串器的HD - SDI的。標(biāo)清SDI
文件頁(yè)數(shù)： 36/55頁(yè)
文件大?。?/td> 922K
GENNUM CORPORATION
27360 - 2
36 of 55
G
3.10.3 SMPTE 352M Payload Identifier
The GS1560A can receive and detect the presence of the
SMPTE 352M payload identifier ancillary data packet. This
four word payload identifier packet may be used to indicate
the transport mechanism, frame rate and line scanning /
sampling structure.
Upon reception of this packet, the device will extract the
four words describing the video format being transported
and make this information available to the host interface via
the four VIDEO_FORMAT_OUT registers (Table 6).
The VIDEO_FORMAT_OUT registers will only be updated if
the received checksum is the same as the locally
calculated checksum.
These registers will be cleared to zero, indicating an
undefined format, if the device loses lock to the input data
stream (LOCKED = LOW), or if the SMPTE_BYPASS pin is
asserted LOW. This is also the default setting after device
reset.
The SMPTE 352M packet should be received once per field
for interlaced systems and once per frame for progressive
systems. If the packet is not received for two complete
video frames, the VIDEO_FORMAT_OUT registers will be
cleared to zero.
3.10.4 Automatic Video Standard and Data Format Detection
The GS1560A can independently detect the input video
standard and data format by using the timing parameters
extracted from the received TRS ID words. This information
is
presented
to
the
VIDEO_STANDARD register (Table 7).
host
interface
via
the
Total samples per line, active samples per line, total lines
per field/frame and active lines per field/frame are also
calculated and presented to the host interface via the
RASTER_STRUCTURE registers (Table 8). These line and
sample count registers are updated once per frame at the
end of line 12. This is in addition to the information
contained in the VIDEO_STANDARD register.
After device reset, the four RASTER_STRUCTURE registers
default to zero.
3.10.4.1 Video Standard Indication
The video standard codes reported in the VD_STD[4:0] bits
of the VIDEO_STANDARD register represent the SMPTE
standards as shown in Table 9.
In addition to the 5-bit video standard code word, the
VIDEO_STANDARD register also contains two status bits.
The STD_LOCK bit will be set HIGH whenever the flywheel
has achieved full synchronization. The INT_PROG bit will be
set HIGH if the detected video standard is progressive and
LOW if the detected video standard is interlaced.
The VD_STD[4:0], STD_LOCK and INT_PROG bits of the
VIDEO_STANDARD register will default to zero after device
reset. These bits will also default to zero if the device loses
lock to the input data stream, (LOCKED = LOW), or if the
SMPTE_BYPASS pin is asserted LOW.
TABLE 6 HOST INTERFACE DESCRIPTION FOR SMPTE 352M PAYLOAD IDENTIFIER REGISTERS
REGISTER NAME
BIT
NAME
DESCRIPTION
R/W
DEFAULT
VIDEO_FORMAT_OUT_B
Address: 013h
15-8
SMPTE352M
Byte 4
Data will be available in this register when Video
Payload Indentification Packets are detected in the
data stream.
R
0
7-0
SMPTE352M
Byte 3
Data will be available in this register when Video
Payload Indentification Packets are detected in the
data stream.
R
0
VIDEO_FORMAT_OUT_A
Address: 012h
15-8
SMPTE352M
Byte 2
Data will be available in this register when Video
Payload Indentification Packets are detected in the
data stream.
R
0
7-0
SMPTE352M
Byte 1
Data will be available in this register when Video
Payload Indentification Packets are detected in the
data stream.
R
0
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