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參數(shù)資料
| 型號： | GS1560A* |
| 英文描述： | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| 中文描述： | 時鐘重計解串器的HD - SDI的。標(biāo)清SDI |
| 文件頁數(shù)： | 34/55頁 |
| 文件大?。?/td> | 922K |
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GENNUM CORPORATION
27360 - 2
34 of 55
G
3.10.2 Ancillary Data Detection and Indication
The GS1560A will detect all types of ancillary data in either
the vertical or horizontal blanking spaces and indicate via
the status signal output pins YANC and CANC the position
of ancillary data in the output data stream. These status
signal outputs are synchronous with PCLK and can be used
as clock enables to external logic, or as write enables to an
external FIFO or other memory device.
When operating in HD mode, (SD/HD = LOW), the YANC
signal will be HIGH whenever ancillary data is detected in
the luma data stream, and the CANC signal will be HIGH
whenever ancillary data is detected in the chroma data
stream.
In SD mode, (SD/HD = HIGH), the YANC and CANC signal
operation will depend on the output data format. For 20-bit
demultiplexed data, (see Section 3.11), the YANC and
CANC signals will operate independently. However, for 10-
bit multiplexed data, the YANC and CANC signals will both
be HIGH whenever ancillary data is detected.
The signals will be HIGH from the start of the ancillary data
preamble and will remain HIGH until after the ancillary data
checksum.
The operation of the YANC and CANC signals is shown in
Figure 12.
Figure 12 YANC and CANC Output Signal Timing
ANC DATA DETECTION - HD 20BIT OUTPUT MODE
ANC DATA DETECTION - HD 10BIT OUTPUT MODE
000
000
000
000
3FF
3FF
3FF
3FF
3FF
3FF
3FF
3FF
DID
YDID
DID
DBN
DBN
ANC DATA
ANC DATA
ANC DATA
ANC DATA
DC
DC
BLANK
BLANK
CSUM
CSUM
CANC
YCSUM
CCSUM
YANC
CANC
PCLK
LUMA DATA OUT
CHROMA DATA OUT
MULTIPLEXED
Y/Cr/Cb DATA OUT
YANC
CANC
PCLK
BLANK
DID
DBN
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
BLANK
CSUM
CSUM
3FF
000
000
DID
3FF
DBN
DC
3FF
3FF
DC
ANC DATA
ANC DATA DETECTION - SD 20BIT OUTPUT MODE
ANC DATA DETECTION - SD 10BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
YANC/CANC
PCLK
LUMA DATA OUT
CHROMA DATA OUT
YANC
CANC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1561* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| GS15T48-5 | 15W DC-DC CONVERTER |
| GS15T48 | |
| GS15T5-5.2 | DC-to-DC Voltage Converter |
| GS15T5-52 | 15W DC-DC CONVERTER FOR ECL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1560ACF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1560ACFE3 | 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80 |
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