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參數(shù)資料
| 型號： | GS1560A* |
| 英文描述： | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| 中文描述： | 時鐘重計解串器的HD - SDI的。標(biāo)清SDI |
| 文件頁數(shù)： | 32/55頁 |
| 文件大?。?/td> | 922K |
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GENNUM CORPORATION
27360 - 2
32 of 55
G
3.8 DVB-ASI FUNCTIONALITY
The GS1560A is said to be in DVB-ASI mode once the
device has detected 32 consecutive DVB-ASI words without
a single word or disparity error being generated. The
device will remain in DVB-ASI mode until 32 consecutive
DVB-ASI word or disparity errors are detected, or until
SMPTE TRS ID words have been detected.
The lock detect block may also drop out of DVB-ASI mode
under the following conditions:
RESET_TRST is asserted LOW
CDx is HIGH
SMPTE_BYPASS is asserted HIGH in slave mode
DVB_ASI is asserted LOW in slave mode
K28.5 sync patterns in the received DVB-ASI data stream
will be detected by the device in either inverted or non-
inverted form.
In master mode, the GS1560A sets the SMPTE_BYPASS pin
LOW and the DVB_ASI pin HIGH to indicate that it has
locked to a DVB-ASI input data stream. When operating in
slave mode, the application layer must set the SD/HD pin
HIGH, in addition to setting SMPTE_BYPASS LOW and
DVB_ASI HIGH, in order to enable DVB-ASI operation.
3.8.1 DVB-ASI 8b/10b Decoding and Word Alignment
After serial-to-parallel conversion, the internal 10-bit data
bus is fed to the DVB-ASI 8b/10b decode and word
alignment block. The function of this block is to word align
the data to the K28.5 sync characters, and 8b/10b decode
and bit-swap the data to achieve bit alignment with the data
outputs.
The extracted 8-bit data will be presented to DOUT[17:10],
bypassing all internal SMPTE mode data processing.
NOTE: When operating in DVB-ASI mode, DOUT[9:0]
become high impedance.
3.8.2 Status Signal Outputs
In DVB-ASI mode, the DOUT19 and DOUT18 pins will be
configured as DVB-ASI status signals SYNCOUT and
WORDERR respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character
is present on the output.
This output may be used to drive
the write enable signal of an external FIFO, thus providing a
means of removing the K28.5 sync characters from the data
stream. Parallel DVB-ASI data may then be clocked out of
the FIFO at some rate less than 27MHz. See Figure 10.
WORDERR will be high whenever the device has detected
a running disparity error or illegal code word.
Figure 10 DVB-ASI FIFO Implementation using the GS1560A
3.9 DATA THROUGH MODE
The GS1560A may be configured by the application layer to
operate as a simple serial-to-parallel converter. In this
mode, the device presents data to the output data bus
without performing any decoding, descrambling or word-
alignment.
Data
MASTER/SLAVE, SMPTE_BYPASS, and DVB_ASI input pins
are set LOW. Under these conditions, the lock detection
algorithm enters PLL lock mode, (see Section 3.6.1), such
that the device may reclock data not conforming to SMPTE
or DVB-ASI streams.
through
mode
is
enabled
only
when
the
When operating in master mode, the GS1560A will set the
SMPTE_BYPASS and DVB_ASI signals to logic LOW if
presented with a data stream without SMPTE TRS ID words
or DVB-ASI sync words. The LOCKED and data bus outputs
will be forced LOW and the serial digital loop-through
output will be a buffered version of the input.
8
8
AOUT ~ HOUT
WORDERR
PCLK = 27MHz
SYNCOUT
DDI
DDI
CLK_IN
CLK_OUT
FIFO
READ_CLK
<27MHz
FE
FF
TS
WE
WORDERR
GS1560A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
| GS1560ACF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1560ACFE3 | 制造商:Semtech Corporation 功能描述:Reclocking deserializer.Receiver for HD/SD/ASI w/ loop through. LQFP80 |
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