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3.10.5.1 Video Standard Error Detection
If a mismatch between the received SMPTE 352M packets
and the calculated video standard occurs, the GS1560A will
indicate a video standard error by setting the VD_STD_ERR
bit of the ERROR_STATUS register HIGH.
3.10.5.2 EDH CRC Error Detection
The GS1560A calculates Full Field (FF) and Active Picture
(AP) CRC words according to SMPTE RP165 in support of
Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the
received CRC values. If a mismatch is detected, the error is
flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of
the ERROR_STATUS register. These two flags are shared
between fields 1 and 2.
The AP_CRC_ERR bit will be set HIGH when an active
picture CRC mismatch has been detected in field 1 or 2.
The FF_CRC_ERR bit will be set HIGH when a full field CRC
mismatch has been detected in field 1 or 2.
EDH CRC errors will only be indicated when the device is
operating in SD mode (SD/HD = HIGH), and when the
device has correctly received EDH packets.
SMPTE RP165 specifies the calculation ranges and scope
of EDH data for standard 525 and 625 component digital
interfaces. The GS1560A will utilize these standard ranges
by default.
If the received video format does not correspond to 525 or
625 digital component video standards as determined by
the flywheel pixel and line counters, then one of two
schemes for determining the EDH calculation ranges will be
employed:
1. Ranges will be based on the line and pixel ranges
programmed by the host interface; or
2. In the absence of user-programmed calculation ranges,
ranges will be determined from the received TRS timing
information.
The registers available to the host interface for
programming EDH calculation ranges include active picture
and full field line start and end positions for both fields.
Table 13 shows the relevant registers, which default to '0'
after device reset.
If any or all of these register values are zero, then the EDH
CRC calculation ranges will be determined from the
flywheel generated H signal. The first active and full field
pixel will always be the first pixel after the SAV TRS code
word. The last active and full field pixel will always be the
last pixel before the start of the EAV TRS code words.
TABLE 12 HOST INTERFACE DESCRIPTION FOR ERROR MASK REGISTER
REGISTER NAME
BIT
NAME
DESCRIPTION
R/W
DEFAULT
ERROR_MASK
Address: 026h
15-11
Not Used
10
VD_STD_ERR_MASK
Video Standard Error Flag Mask bit.
R/W
0
9
FF_CRC_ERR_MASK
Full Field CRC Error Flag Mask bit.
R/W
0
8
AP_CRC_ERR_MASK
Active Picture CRC Error Flag Mask bit.
R/W
0
7
LOCK_ERR_MASK
Lock Error Flag Mask bit.
R/W
0
6
CCS_ERR_MASK
Chroma Checksum Error Flag Mask bit.
R/W
0
5
YCS_ERR_MASK
Luma Checksum Error Flag Mask bit.
R/W
0
4
CCRC_ERR_MASK
Chroma CRC Error Flag Mask bit.
R/W
0
3
YCRC_ERR_MASK
Luma CRC Error Flag Mask bit.
R/W
0
2
LNUM_ERR_MASK
Line Number Error Flag Mask bit.
R/W
0
1
SAV_ERR_MASK
Start of Active Video Error Flag Mask bit.
R/W
0
0
EAV_ERR_MASK
End of Active Video Error Flag Mask bit.
R/W
0