參數(shù)資料
型號： GMS87C7216LQ
廠商： Electronic Theatre Controls, Inc.
元件分類： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 85/121頁
文件大?。?/td> 1645K
代理商： GMS87C7216LQ
GMS81C7208/7216
FEB. 2005 Ver 1.04
81
22. RESET
The GMS81C7208/16 has two types of reset generation proce-
dures; one is an external reset input, the other is a watch-dog tim-
er reset. Table 22-1 shows on-chip hardware initialization by
reset action.
Figure 22-1 Simple Power-On Reset Circuit.
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset in accomplished by holding the RESET pin low
for at least 8 oscillator periods, within the operating voltage range
and oscillation stable, it is applied, and the internal state is initial-
ized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods
are required to start execution as shown in Figure 22-2.
Internal RAM is not affected by reset. When V
DD
is turned on,
the RAM content is indeterminate. Therefore, this RAM should
be initialized before read or tested it.
When the RESET pin input goes to high, the reset operation is re-
leased and the program execution starts at the vector address
stored at addresses FFFE
H
- FFFF
H
.
A connection for simple power-on-reset is shown in Figure .
Figure 22-2 Timing Diagram after RESET
22.2 Watchdog Timer Reset
Refer to “18. LCD DRIVER” on page 65.
7036P
V
CC
10uF
+
10k
to the RESET pin
On-chip Hardware
Initial Value
Program Counter (PC)
(FFFF
H
) - (FFFE
H
)
G-Flag (G)
0
Operation Mode
Main Operating Mode
Peripheral Clock
On
Watchdog Timer
Disable (Because the Watch
timer is disabled)
Control Registers
Refer to Table 8-1 on
page 24
Low Voltage Detector
Enable
Table 22-1 Initializing Internal Status by Reset Action
MAIN PROGRAM
Oscillator
(X
IN
pin)
FFFE FFFF
Stabilization Time
t
ST
= 62.5mS at 4.19MHz
RESET
ADDRESS
BUS
DATA
BUS
1
2
3
4
5
6
7
Start
FE
ADL
ADH
OP
RESET Process Step
~
~
~
~
~
t
ST
=
x 256
f
MAIN
÷
1024
1
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