參數資料
型號： GMS87C7216LQ
廠商： Electronic Theatre Controls, Inc.
元件分類： 數學處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數： 78/121頁
文件大?。?/td> 1645K
代理商： GMS87C7216LQ
GMS81C7208/7216
74
FEB. 2005 Ver 1.04
Figure 19-2 WTMR, WDTR: Watch Timer and Watchdog Timer Data Register
Example: Sets the Watchdog Timer Detection Time to 1 SEC at 4.19MHz
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDEN (bit 4 in CKCTLR)
to “1”. WDEN is initialized to “1” during reset and it should be
clear to “0” disable.
Example: Enables watchdog timer for Reset
:
LDM
LDM
:
WTMR,#0100_XXXXB;
WTEN
←
1
WDTR,#00X1_XX11B;
WDEN
←
1
The watchdog timer is disabled by clearing either bit 4 (WDEN)
of WDTR or bit 6 (WTEN) of WTMR. The watchdog timer is
halted in STOP mode and restarts automatically after STOP mode
is released.
Clearing 2-Bit Binary Counter of the Watchdog
Timer
The watchdog timer count the clock source as 14-bit binary
INITIAL VALUE: -0--_0000
B
ADDRESS: 0EF
H
WTMR
-
-
WTEN
WTIN1 WTIN0
-
R/W
R/W
R/W
-
R/W
R/W
-
-
WTCK1 WTCK0
Clock Source Selection
00: Reserved
01: Main Clock (f
XIN
÷
128)
10: Main Clock (test purpose in factory)
11: -
Watch Timer Interrupt Interval Selection
00: 16Hz
01: 4Hz
10: 2Hz
11: -
Watch Timer Count Enable
0: Disable
1: Enable
INITIAL VALUE: --01_0010
B
ADDRESS: 0DF
H
WDTR
-
-
WDCK1 WDCK0
R/W
R/W
R/W
-
-
R/W
-
WDEN
WDOM
WDCLR
Watchdog Timer Interrupt Interval Selection
00: 2 sec.
01: 1 sec.
10: 0.5 sec.
11: 0.25 sec.
R/W
R/W
Clear Bit
0: Normal operation
1: Clear and starts counting
When
f
XIN
= 4.19MHz
Output Mode
0: Interrupt Request
1: Reset CPU
Watchdog Timer Count Enable
0: Disable
1: Enable
When
f
XIN
= 4.19MHz
LDM
LDM
WTMR,#0100_1000B;
Select sub clock as an input source
WDTR,#0001_0111B
SET1
:
:
:
:
SET1
:
:
SET1
WDCLR
;
Clear counter
WDCLR
;
Clear counter
WDCLR
;
Clear counter
Within 0.75 sec.
Within 0.75 sec.
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