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參數(shù)資料
| 型號： | GMS87C7216LQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 63/121頁 |
| 文件大?。?/td> | 1645K |
| 代理商： | GMS87C7216LQ |
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GMS81C7208/7216
FEB. 2005 Ver 1.04
59
17. INTERRUPTS
The GMS81C7208/16 interrupt circuits consist of interrupt en-
able register (IENH, IENL), interrupt request flags of IRQH,
IRQL, priority circuit, and master enable flag (“I” flag of PSW).
twelve interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 17-2.
The basic interval timer interrupt is generated by BITIF which is
set by an overflow in the timer register.
The watchdog timer interrupt is generated by WDTIF which set
by a match in watchdog timer register.
The external interrupts INT0 ~ INT2 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF and INT2IF in register IRQH and IRQL. When an exter-
nal interrupt is generated, the flag that generated it is cleared by
the hardware when the service routine is vectored to only if the
interrupt was transition-activated.
The timer 0 ~ timer 3 interrupts are generated by T0IF~T3IF
which are set by a match in their respective Timer/Counter regis-
ter.
The serial communication interrupts are generated by SIOIF
which is set by 8-bit serial data transmitting or receiving through
SCK, SIN, SOUT pin.
The AD converter interrupt is generated by ADIF which is set by
finishing the analog to digital conversion.
The watch timer interrupt is generated by WTIF which is set by
an 14-bit binary counter overflow.
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW on page 18), the interrupt enable register
(IENH, IENL), and the interrupt request flags (in IRQH and
IRQL) except power-on reset and software BRK interrupt. Below
table shows the Interrupt priority.
Vector addresses are shown in Figure 8-6 on page 20. Interrupt
enable registers are shown in Figure 17-3. These registers are
composed of interrupt enable flags of each interrupt source and
these flags determines whether an interrupt will be accepted or
not. When enable flag is “0”, a corresponding interrupt source is
prohibited. Note that PSW contains also a master enable bit, I-
flag, which disables all interrupts at once.
Figure 17-1 Interrupt Request Flag
Reset/Interrupt
Symbol
Priority
Hardware Reset
Reserved
Basic Interval Timer
Watchdog Timer
External Interrupt 0
External Interrupt 1
Timer/Counter 0
Timer/Counter 1
External Interrupt 2
Serial Communication
ADC Interrupt
Watch Timer Interrupt
Timer/Counter 2
Timer/Counter 3
RESET
-
BIT
WDT
INT0
INT1
Timer 0
Timer 1
INT2
SCI
ADC
WT
Timer 2
Timer 3
-
1
2
3
4
5
6
7
8
9
10
11
12
13
WDTIF
R/W
-
Timer/Counter 3
Timer/Counter 2
Watch Timer
INITIAL VALUE: -000 0000
B
ADDRESS: 0DD
H
IRQH
-
MSB
LSB
T0IF
T1IF
INT0IF INT1IF
BITIF
R/W
R/W
Timer/Counter 1 Interrupt Request Flag
Timer/Counter 0
External Interrupt 1
External Interrupt 0
Serial Communication
INITIAL VALUE: 0--0 0000
B
ADDRESS: 0DC
H
IRQL
MSB
LSB
R/W
R/W
-
R/W
R/W
Basic Interval Timer
Watchdog Timer
A/D Converter
SIOIF
-
INT2IF
-
T2IF
T3IF
ADIF
WTIF
-
R/W
R/W
R/W
R/W
R/W
-
R/W
External Interrupt 2
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