參數(shù)資料
型號(hào)： GMS87C7216LQ
廠商： Electronic Theatre Controls, Inc.
元件分類： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁數(shù)： 53/121頁
文件大?。?/td> 1645K
代理商： GMS87C7216LQ
GMS81C7208/7216
FEB. 2005 Ver 1.04
49
13.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit Timer/
Counter register T0, T1 are incremented from 0000
H
until it
matches TDR0, TDR1 and then resets to 0000
H
. The match out-
put generates Timer 0 interrupt.
The clock source of the Timer 0 is selected either internal or ex-
ternal clock by bit T0SL1, T0SL0.
Even if the Timer 0 (including the Timer 1) is used as a 16-bit
timer, the Timer 2 and Timer 3 can still be used as either two 8-
bit timer or one 16-bit timer by setting the TM2. Reversely, even
if the Timer 2 (including the Timer 3) is used as a 16-bit timer,
the Timer 0 and Timer 1 can still be used as 8-bit timer indepen-
dently.
Figure 13-9 16-bit Timer/Counter
T0IF
clear
0: Stop
1: Clear and start
T0ST
T0CK[2:0]
TIMER 0 INTERRUPT
(Not Timer 1 interrupt)
T0CN
Comparator
TIMER 0 + TIMER 1
→
TIMER 0 (16-bit)
Higher byte
Lower byte
COMPARE DATA
T0
(16-bit)
1
0
7
-
6
-
5
4
3
2
1
0
INITIAL VALUE: 00
H
ADDRESS: 0E0
H
TM0
X
X
X
X
X
X
0
X
X means don’t care
÷
2
÷
4
÷
8
MUX
P
000
001
010
÷
32
÷
128
÷
512
÷
2048
011
100
101
110
111
Edge Detector
EC0 PIN
TM1
BTCL
T1CK1
X
1
0
0
1
1
X
X
-
-
INITIAL VALUE: 00
H
ADDRESS: 0E2
H
T1CK0 T1CN T1ST
16BIT0
CAP1
BTCL
T0CK1T0CK0 T0CN T0ST
CAP0
T0CK2
7
-
6
-
5
4
3
2
1
0
INITIAL VALUE: 00
H
ADDRESS: 0E6
H
TM2
X
X
X
X
X
X
0
X
TM3
BTCL
T3CK1
X
1
0
0
1
1
X
X
-
-
INITIAL VALUE: 00
H
ADDRESS: 0E8
H
T3CK0 T3CN T3ST
16BIT1
CAP3
BTCL
T2CK1T2CK0 T2CN T2ST
CAP2
T2CK2
T1
TDR0
TDR1
f
XIN
reserved
0X
1X
SCMR[1:0]
T2IF
clear
0: Stop
1: Clear and start
T2ST
T2CK[2:0]
TIMER 2 INTERRUPT
(Not Timer 3 interrupt)
T2CN
Comparator
TIMER 0 + TIMER 1
→
TIMER 0 (16-bit)
Higher byte
Lower byte
COMPARE DATA
T2
(16-bit)
1
0
÷
2
÷
4
÷
8
MUX
P
000
001
010
÷
32
÷
128
÷
512
÷
2048
011
100
101
110
111
Edge Detector
EC2 PIN
T3
TDR2
TDR3
f
XIN
reserved
1X
1X
SCMR[1:0]
X means don’t care
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