參數(shù)資料
型號(hào)： GMS87C7216LQ
廠(chǎng)商： Electronic Theatre Controls, Inc.
元件分類(lèi)： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 46/121頁(yè)
文件大?。?/td> 1645K
代理商： GMS87C7216LQ
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GMS81C7208/7216
42
FEB. 2005 Ver 1.04
13. TIMER/EVENT COUNTER
The GMS81C7208/16 has four Timer/Event Counters. Each
module can generate an interrupt to indicate that an event has oc-
curred (i.e. timer match).
Timer 0 and timer 1 are can be used either two 8-bit Timer/
Counter or one 16-bit Timer/Counter with combine them. Also
timer 2 and timer 3 can be joined as a 16-bit Timer/Counter.
In the “timer” function, the register is increased every internal
clock input. Thus, one can think of it as counting internal clock
input. The count rate is 1/2 to 1/2048 of the oscillator frequency.
In the “counter” function, the register is incremented in response
to a 0-to-1 (rising edge) transition at its corresponding external
input pin, EC0 or EC2 pin.
In addition the “capture” function, the register is incremented in
response external or internal clock sources same with timer or
counter function. When external clock edge input, the count reg-
ister is captured into capture data register correspondingly.
It has five operating modes: “8-bit Timer/Counter”, “16-bit Tim-
er/Counter”, “8-bit capture”, “16-bit capture” which are selected
by bit in timer mode register TM
n
.
In operation of timer 2, timer 3, their operations are same with
timer 0, timer 1, respectively.
When programming the software, you may refer to following ex-
ample
.
Example 1:
Timer 0 = 8-bit timer mode, 8ms interval at 4MHz
Timer 1 = 8-bit timer mode, 4ms interval at 4MHz
Timer 2 = 16-bit event counter mode
LDM
LDM
LDM
LDM
LDM
SCMR,#0
TDR0,#249
TM0,#0001_0011B
TDR1,#124
TM1,#0000_1111B
;Main clock mode
LDM
LDM
LDM
LDM
TDR2,#1FH
TDR3,#4CH
TM2,#0001_1111B
TM3,#0100_1100B
SET1
SET1
EI
:
:
T0E
T2E
Example 2:
Timer0 = 16-bit timer mode, 0.5s at 4MHz
Timer2 = 2ms 8-bit timer mode at 4MHz
Timer3 = 250us 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
SCMR,#0
TDR0,#23H
TDR1,#0F4H
TM0,#0FH
TM1,#4CH
;Main clock mode
;FXIN/32, 8us
LDM
LDM
LDM
LDM
TDR2,#249
TDR3,#124
TM2,#0FH
TM3,#0DH
;FXUN/32, 8us
;FXIN/8, 2us
SET1
SET1
SET1
EI
:
:
T0E
T2E
T3E
Example 3:
Timer0 = 8-bit timer mode, 2ms interval at 4MHz
Timer1 = 8-bit capture mode, 2us sampling count.
LDM
LDM
TDR0,#249
TM0,#0FH
;250x8=2000us
;FXIN/32, 8us
LDM
LDM
LDM
LDM
IEDS,#XXXX_01XXB ;FALLING
PMR,#XXXX_XX1XB ;AS INT1
TDR1,#0FFH
TM1,#0001_1011B ;2us
SET1
SET1
SET1
EI
:
:
T0E
T1E
INT1E
;ENABLE TIMER 0
;ENABLE TIMER 1
;ENABLE EXT. INT1
X: don’t care.
Example 4:
Timer0 = 8-bit timer mode, 2ms interval at 4MHz
Timer2 = 16-bit capture mode, 8us sampling count.
LDM
LDM
TDR0,#249
TM0,#0FH
LDM
LDM
LDM
LDM
LDM
LDM
IEDS,#XX11_XXXXB
PMR4,#XXXX_X1XXB
TDR2,#0FFH ;MAX
TDR3,#0FFH ;MAX
TM2,#XX10_1111B ;/32
TM3,#X10X_11XXB
SET1
SET1
SET1
EI
:
:
T0E
T2E
INT2E
;ENABLE TIMER 0
;ENABLE TIMER 2
;ENABLE EXT. INT2
X: don’t care.
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