參數(shù)資料
型號(hào)： GMS87C7216LQ
廠商： Electronic Theatre Controls, Inc.
元件分類： 數(shù)學(xué)處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8位單晶片微控制器
文件頁(yè)數(shù)： 82/121頁(yè)
文件大小： 1645K
代理商： GMS87C7216LQ
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GMS81C7208/7216
78
FEB. 2005 Ver 1.04
Figure 20-4 STOP Mode Release Timing by External Interrupt
Figure 20-5 STOP Mode Release Timing by RESET
Minimizing Current Consumption
The stop mode is designed to reduce power consumption.
To minimize current drawn during stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
Note:
In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(V
DD
/V
SS
); however, when the input level becomes higher
than the power voltage level (by approximately 0.3V), a cur-
rent begins to flow. Therefore, if cutting off the output tran-
sistor at an I/O port puts the pin signal into the high-
impedance state, a current flow across the ports input tran-
sistor, requiring it to fix the level by pull-up or other means.
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Oscillator
(X
IN
pin)
~
n
0
BIT Counter
n+1
n+2
n+3
~
Normal Operation
Stop Operation
Normal Operation
1
FE
FF
0
1
2
~
~
~
t
>
20ms
by software
~
~
External Interrupt
Internal Clock
Clear
STOP Instruction
Executed
~
~
~
Oscillator
(X
IN
pin)
~
n
0
BIT Counter
n+1
n+2
n+3
~
Normal Operation
Stop Operation
Normal Operation
1
FE
FF
0
1
2
~
~
~
t
> 62.5ms
at 4.19MHz by hardware
Internal Clock
Clear
STOP Instruction
Executed
~
~
~
RESET
n+2
t
ST
=
x 256
f
MAIN
÷
1024
1
~
~
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