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| 型號(hào)： | GMS87C7216LQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 77/121頁(yè) |
| 文件大小： | 1645K |
| 代理商： | GMS87C7216LQ |
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GMS81C7208/7216
FEB. 2005 Ver 1.04
73
19. WATCH / WATCHDOG TIMER
19.1 Watch Timer
The watch timer goes the clock continuously even during the
power saving mode. When MCU is in the Stop or Sleep mode,
MCU can wake up itself every 2Hz or 4Hz or 16Hz.
The watch timer consists of input clock selector, 14-bit binary
counter, interval selector and watch timer mode register WTMR
(address 0EF
H
). The WTMR is 5-bit read/write register and
shown in Figure 19-2. WTMR can select the clock input by 2 bits
WTCK[1:0] and interval time selector by 2 bits WTIN[1:0] and
enable/disable bit. The WTEN bit is set to “1” timer start count-
ing. Input clocks can be selected among three different source
which are divided main clock (f
XIN
÷
128) or main clock. Recom-
mend the oscillator 4.194304MHz as a main. Because above
main frequency is equal to 128 times of 32.768kHz. Generally
main clock (f
XIN
) at WTCK=10
B
is not be used, it is just for test
purpose in factory.
In the Stop Mode, the main clock is stopped.
LDM
EI
LDM
IENL,#XXXX_X1XXB
WTMR,#0100_1000B
Figure 19-1 Block Diagram of Watchdog Timer
19.2 Watchdog Timer
The watchdog timer rapidly detects the CPU malfunction such as
endless looping caused by noise or the like, and resumes the CPU
to the normal state.
The watchdog timer signal for detecting malfunction can be se-
lected either a reset CPU or a interrupt request as you want.
When the watchdog timer is not being used for malfunction de-
tection, it can be used as a timer to generate an interrupt at fixed
intervals.
Watchdog Timer Control
Figure 19-2 shows the watchdog timer control register WDTR
(address 0DF
H
). The watchdog timer is automatically enabled
initially and watchdog output to reset CPU but clock input source
is disabled. To enable this function, you should write bit WTEN
of WTMR (address 0EF
H
) set to “1”.
The CPU malfunction is detected during setting of the detection
time, selecting of output, and clearing of the binary counter.
Clearing the 2-bit binary counter by bit WDCLR of WDTR is re-
peated within the detection time.
If the malfunction occurs for any cause, the watchdog timer out-
put will become active from the binary counters unless the binary
counter is cleared. At this time, when WDOM=1, a reset is gen-
erated, which drives the RESET pin to low to reset the internal
hardware. When WDOM=0, a watchdog timer interrupt (WD-
TIF) is generated instead of Reset function. This interrupt can be
used general timer as user want.
When main clock is selected as clock input source on the STOP
mode, clock input is stopped so the watchdog timer temporarily
stops counting.
enable
Watch Timer interrupt
WTIF
0
1
14-bit Binary Counter
MUX
11
reserved
f
XIN
÷
128
f
XIN
(test)
f
W
f
XIN
= 4.194304 MHz
Interval Selector
2
4
1
2
4
8
1
2-bit Binary Counter
WDCK[1:0]
WTIN[1:0]
WTCK[1:0]
c
0: Stop
1: Clear and start
WDCLR
WDTIF
to RESET CPU
Watchdog Timer Interrupt
overflow
WDEN
WDOM
00
01
10
00
01
10
00
01
10
enable
0
1
WTEN
MUX
When
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