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參數(shù)資料
| 型號： | GCIXF440ACT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 59/128頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF440ACT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
59
4.0
IX Bus Interface Operation
This section describes the IXF1002 IX Bus interface operation, including the transmission and
reception flows.
4.1
IX Bus Interface
The IXF1002 uses a generic bus interface for data transfer to and from its FIFOs. The data bus is 64
bits wide and has three modes of operation. Big and little endian byte ordering are both supported
on 32-bit boundaries (PORT_MODE<BEND>). The different FIFOs are accessed according to
port selection signal (fps) as well as transmit or receive enabling signals (txsel_l, rxsel_l). Data
transfer is synchronized to the main clock (clk), and new data may be sent or received on each
clock cycle. Each FIFO has a dedicated signal for each direction (txrdy, rxrdy), reporting if it is
ready for data transfer according to predetermined thresholds. (FFO_TSHD<TTH,RTH>). The
burst size should be shorter than or equal to the effective threshold. The amount of data transferred
during a FIFO access may be dynamically changed from one access to the other. On receive, if the
PORT_MODE<HRYD> bit is reset, each first burst of a packet should be shorter than or equal to
the header size.
4.1.1
IX Bus Operating Modes
The IXF1002 provides three IX Bus modes:
—
Full-64 mode
–
64 bits for transmit or receive
—
Split mode
–
32 low bits for receive, and 32 high bits for transmit
—
Narrow mode
–
32 bits for transmit or receive
The selection of the IX Bus mode is done through the FIFMD field in the PORT_MODE register,
as detailed in
Section 3.2.3.3
.
4.1.1.1
Signal Naming in Full-64 and Narrow Mode
When the IX Bus is in full-64 or narrow mode, signals fps, sop and eop are input during assertion
of the txsel_l signal, and are output during assertion of the rxsel_l signal. In full-64 and narrow
mode, fps_txf, sop_txf and eop_txf are not used and should be connected to pull-up resistors.
4.1.1.2
Signal Naming in Split Mode
When the IX Bus is in split mode, the three signals fps, sop and eop which are output signals, refer
to the packets being received on the 32 low bits of the IX Bus. These three signals are then named
fps_rxf, sop_rxf and eop_rxf. Three other input signals fps_txf, sop_txf and eop_txf refer to the
packets being transmitted on the 32 high bits of the IX Bus.
Figure 2, Figure 3
and
Figure 4
show
the signals of the parallel interface, depending on the different FIFO modes.
Note:
When working in split-bus mode in port 1 only, there is a need to write both port
’
s PORT_MODE
registers.
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