參數(shù)資料
型號： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 23/128頁
文件大?。?/td> 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
23
3.2.2
Base Registers
The following sections describe the individual base registers.
3.2.2.1
Interrupt Status Register
Mnemonic: INT_STT
Address: 00H
–
01H
The interrupt status register handles information regarding events that cause an interrupt. A specific
event sets a bit if it was programmed to generate an interrupt in the interrupt enable register (INT_EN).
Reading this register will reset all the bits, except for PKEV and OVFC bits. These bits are reset
only when the asserted bits in the relevant status registers are reset by read.
Bit Name
—
Bit #
15
Bit Description
RESERVED
Port stop.
Indicates that transmit or receive path is in the stop state, following disable programming in
the port control register. If both transmit and receive paths are programmed to be stopped,
this bit is set when they both reach the stop state.
Counter overflow.
Indicates that at least one network statistic counter has reached its highest possible value. This
bit is a logical OR of all bits in the counter overflow status registers (see
Section 3.2.2.6
and
Section 3.2.2.7
).
Link change.
Indicates that a link change has occurred while working in GPCS mode. The actual link
status is reported in the GMII status register GMII_STT<LNKSTT> (see
Section 3.2.5.2
).
RESERVED
Transmit OK.
Indicates successful packet transmission.
Packet event.
A logical OR of all the bits in the transmit and receive status register (TX_RX_STT),
excluding the packet count (PKC) bits. Upon receive events, this bit is set only after the
packet is fully received by the chip.
Receive OK.
Indicates that a packet has been received without error. This bit is set only after the packet
is fully received by the chip.
Auto-Negotiation error.
Indicates that the link partner advertises that it does not support full-duplex operation, and
that Auto-Negotiation was restarted.
Page received.
Indicates that a base or next page has been received during Auto-Negotiation process.
RESERVED
STOP
14
OVFC
13
LNCH
12
—
11
TXOK
10
PKEV
9
RXOK
8
ANER
7
PGRC
6
—
5:0
A4966-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
T
O
P
O
V
F
C
L
N
C
H
T
X
O
K
P
K
E
V
R
X
O
K
A
N
E
R
P
G
R
C
相關(guān)PDF資料
PDF描述
GCIXP1250-166 Microprocessor
GCIXP1250-200 Microprocessor
GCIXP1250-232 Microprocessor
GCK101 Analog IC
GCK131 Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GCIXP1200EB 功能描述:IC NETWRK PROCESSR 200MHZ 432BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
GCIXP1200FC 功能描述:IC NETWRK PROCESSR 232MHZ 432BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
GCIXP1200GA 功能描述:IC MPU NETWORK 166MHZ 432-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
GCIXP1200GB 功能描述:IC MPU NETWORK 200MHZ 432-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
GCIXP1200GC 功能描述:IC MPU NETWORK 232MHZ 432-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*