參數(shù)資料
型號： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 25/128頁
文件大?。?/td> 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
25
The port control register handles all the control bits of the port.
Bit Name
Bit #
Bit Description
—
15:9
RESERVED
FCT
8
Flow-control packet trigger.
When set, initiates a flow-control packet transmission to the remote node, as defined in the
802.3x IEEE Standard. The pause time field in the transmitted packet will be copied from
the PAUSE_TIME register (see
Section 3.2.3.6
).
—
7:6
RESERVED
TXSTT
5
Transmit restart.
When set, the chip restarts the transmission process after stopping due to a transmit error.
The TXSTT is a trigger bit (does not require reset before setting).
TXEN
4
Transmit enable.
When this bit is set, the port enters the transmit working mode. When reset, the port
completes transmission of the packet currently processed, and then stops. Stop state is
reported in the STOP bit located in the interrupt status register (INT_STT).
RXEN
3
Receive enable.
When this bit is set, the port enters the receive working mode. When reset, the port
completes reception of the packet currently processed, and then stops. Stop state is
reported in the STOP bit located in the interrupt status register (INT_STT).
PTRST
2
Port reset.
When set, this bit causes the transmit and receive logic to reset. setting this bit will not
reset the control registers.
CTRST
1
Control reset.
When set, this bit resets all the registers, except PORT_CTR, to their default values.
Transmit and receive logic are also reset.
This bit is not self clearing, it requires set and then reset.
CNRST
0
Counter reset.
When set, this bit resets all the network statistic counters. The CNRST is a trigger bit (does
not require resetting before setting.)
Access Rules
Register
access
R/W
Bit 5 and Bit 8 are trigger bits and are Write only.
Value
after
reset
0000H
A4968-01
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
F
C
T
T
X
E
N
T
X
S
T
T
R
X
E
N
P
T
R
S
T
C
T
R
S
T
C
N
R
S
T
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