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Datasheet
iii
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Contents
1.0
Introduction.........................................................................................................................9
1.1
General Description...............................................................................................9
1.2
Block Diagram.......................................................................................................9
1.3
Hardware Overview.............................................................................................10
2.0
Pinout...............................................................................................................................11
2.1
Signal Description ...............................................................................................11
2.2
Pin Count.............................................................................................................17
2.3
Connection Rules................................................................................................17
2.4
Pin List.................................................................................................................18
3.0
Registers Description.......................................................................................................21
3.1
Register Conventions..........................................................................................21
3.1.1
Access Rules..........................................................................................21
3.2
CSR Register ......................................................................................................22
3.2.1
Register Mapping...................................................................................22
3.2.2
Base Registers.......................................................................................23
3.2.2.1 Interrupt Status Register ...........................................................23
3.2.2.2 Interrupt Enable Register ..........................................................24
3.2.2.3 Port Control Register.................................................................24
3.2.2.4 Identification and Revision Register..........................................26
3.2.2.5 Transmit and Receive Status Register......................................26
3.2.2.6 Transmit Counter Overflow Status Register..............................27
3.2.2.7 Receive Counter Overflow Status Register...............................28
3.2.3
Configuration Registers..........................................................................30
3.2.3.1 Transmit and Receive Error Mode Register..............................30
3.2.3.2 FIFO Threshold Register...........................................................31
3.2.3.3 Port Working Mode Register .....................................................32
3.2.3.4 Transmit and Receive Parameters Register .............................34
3.2.3.5 Transmit Threshold Register.....................................................35
3.2.3.6 Transmit Flow-Control Pause Time Register ............................35
3.2.3.7 Maximum Packet Size Register ................................................37
3.2.3.8 Inter Packet Gap Value Register...............................................37
3.2.3.9 MAC Address Registers............................................................38
3.2.3.10VLAN Tag Length/Type Register ..............................................38
3.2.3.11Transmit Counter Overflow Mask Register ...............................39
3.2.3.12Receive Counter Overflow Mask Register ................................41
3.2.4
GMII Management Access Registers.....................................................42
3.2.4.1 GMII Management Access Register..........................................42
3.2.4.2 GMII Management Data Register..............................................44
3.2.5
GMII Management Register Set.............................................................45
3.2.5.1 GMII Control Register................................................................45
3.2.5.2 GMII Status Register.................................................................46
3.2.5.3 AN Advertisement Register.......................................................48
3.2.5.4 AN Link Partner Ability Base Page Register .............................49
3.2.5.5 AN Expansion Register .............................................................50
3.2.5.6 AN Next Page Register .............................................................51
3.2.5.7 AN Link Partner Receive Next Page Register...........................52