參數(shù)資料
型號： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 57/128頁
文件大?。?/td> 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
57
3.3.2
Network Statistic Counters Access Rules
The network statistic counters access rules are as follows:
The counters can be accessed with a base address equal to 100H or 200H. Accessing the
counters with the 100H base address causes them to reset. Accessing them with the 200H will
not reset the counter.
When the CPU data bus is in 16 bit mode, access to network statistic counters should be done
only with even numbered addresses.
The counters must be read from the lower to the upper bytes, in consecutive accesses.
The statistic counters are not writable.
Note:
When a counter reaches its highest possible value, it will continue to count from zero, and the
corresponding counter overflow status bit will be set.
Note:
Receive statistic counters are updated even if the receive FIFO overflows.
Note:
All the byte counters take CRC bytes into account, but exclude the framing bits in the packets.
3.4
Access Sequences
This section describes the initialization, mode change, and interrupt handling sequences for the
IXF1002.
3.4.1
Initialization Sequence
Each IXF1002 port must be initialized according to the following sequence:
1. Disable the port and reset it by writing a value of 07h to the port control register (PORT_CTR)
and then writing 00h to clear the reset.
2. Initialize the port by writing to the relevant configuration registers.
3. Enable port operation by writing a value of 18h to the port control register (PORT_CTR).
3.4.2
Mode Change Sequence
In order to change the IXF1002 working mode without impacting packet transfer, the following
sequence must be used:
1. Disable the port by writing a value of 00h to the port control register (PORT_CTR).
2. Wait until the port enters the stop state. The stop state entry may generate an interrupt if
enabled, and is reported by the stop bit in the interrupt status register (INT_STT<STOP>).
3. Change the configuration register values.
4. Enable port operation by writing a value of 18h to the port control register (PORT_CTR).
Note:
The port mode register (PORT_MODE) can be updated only by using the initialization sequence.
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