參數(shù)資料
型號： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 4/128頁
文件大?。?/td> 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
iv
Datasheet
3.2.5.8 Extended Status Register..........................................................53
3.2.5.9 GPCS Status Register...............................................................54
Network Statistic Counter Mapping.....................................................................55
3.3.1
Register Mapping...................................................................................55
3.3.2
Network Statistic Counters Access Rules..............................................57
Access Sequences..............................................................................................57
3.4.1
Initialization Sequence ...........................................................................57
3.4.2
Mode Change Sequence .......................................................................57
3.4.3
Interrupt Handling Sequence .................................................................58
3.3
3.4
4.0
IX Bus Interface Operation...............................................................................................59
4.1
IX Bus Interface...................................................................................................59
4.1.1
IX Bus Operating Modes........................................................................59
4.1.1.1 Signal Naming in Full-64 and Narrow Mode..............................59
4.1.1.2 Signal Naming in Split Mode.....................................................59
4.1.2
Byte Ordering on IX Bus ........................................................................60
4.1.3
FIFO Status Signaling............................................................................62
4.2
Packet Transmission...........................................................................................62
4.2.1
Packet Loading ......................................................................................62
4.2.2
VLAN Tagging........................................................................................63
4.2.2.1 VLAN Tag Functions in IXF1002...............................................64
4.2.2.2 VLAN Tag Append ....................................................................64
4.2.2.3 VLAN Tag Strip .........................................................................65
4.2.2.4 VLAN Tag Replace....................................................................66
4.2.3
Network Transmission............................................................................66
4.2.4
FIFO Underflow......................................................................................66
4.2.4.1 Stopping Mode on Transmission Underflow Error.....................67
4.2.5
Transmit Flow Diagram..........................................................................67
4.3
Packet Reception................................................................................................68
4.3.1
Packet Storing........................................................................................68
4.3.1.1 Packet Status............................................................................69
4.3.2
Header Preprocessing ...........................................................................69
4.3.3
Packet Segmentation.............................................................................70
4.3.4
Packet Abortion......................................................................................71
4.3.5
Network Reception.................................................................................71
4.3.6
Rejecting Mode on Reception Errors .....................................................71
4.3.7
Accepting Mode on Reception Errors.....................................................71
4.3.8
Receive Flow Diagram...........................................................................72
5.0
CPU Interface Operation..................................................................................................73
5.1
CPU Interface......................................................................................................73
5.2
Network Management.........................................................................................73
5.2.1
SNMP MIB Support................................................................................74
5.2.2
RMON Statistic Group Support..............................................................74
5.2.3
RMON Host Group Support ...................................................................75
6.0
Network Interface Operation............................................................................................77
6.1
Operating Modes.................................................................................................77
6.2
GMII Port Interface..............................................................................................78
6.3
MAC Frame Format ............................................................................................79
6.4
MAC Transmit Operation ....................................................................................80
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