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參數(shù)資料
| 型號： | FW32305 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機控制器接口 |
| 文件頁數(shù)： | 17/152頁 |
| 文件大?。?/td> | 1625K |
| 代理商： | FW32305 |
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Agere Systems Inc.
17
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
101
Symbol*
TPBIAS2
* Active-low signals within this document are indicated by an N following the symbol names.
Type
Description
Analog I/O
Port 2, Twisted-Pair Bias.
TPBIAS2 provides the
1.86 V nominal bias voltage needed for proper opera-
tion of the twisted-pair cable drivers and receivers and
for sending a valid cable connection signal to the
remote nodes.
Analog Circuit Ground.
All V
SSA
signals should be
tied together to a low-impedance ground plane.
Analog Circuit Ground.
All V
SSA
signals should be
tied together to a low-impedance ground plane.
Analog Circuit Ground.
V
DDA
supplies power to the
analog portion of the device.
Port 1, Port Cable Pair B.
TPB1± is the port B connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 1, Port Cable Pair A.
TPA1± is the port A connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 1, Twisted-Pair Bias.
TPBIAS1 provides the
1.86 V nominal bias voltage needed for proper opera-
tion of the twisted-pair cable drivers and receivers and
for sending a valid cable connection signal to the
remote nodes.
Port 0, Port Cable Pair B.
TPB0± is the port B connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 0, Port Cable Pair A.
TPA0± is the port A connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 0, Twisted-Pair Bias.
TPBIAS0 provides the
1.86 V nominal bias voltage needed for proper opera-
tion of the twisted-pair cable drivers and receivers and
for sending a valid cable connection signal to the
remote nodes.
Analog Circuit Ground.
All V
SSA
signals should be
tied together to a low-impedance ground plane.
Analog Circuit Power.
V
DDA
supplies power to the
analog portion of the device.
102
V
SSA
—
103
V
SSA
—
104
V
DDA
—
105
TPB1–
Analog I/O
106
TPB1+
107
TPA1–
Analog I/O
108
TPA1+
109
TPBIAS1
Analog I/O
110
TPB0–
Analog I/O
111
TPB0+
112
TPA0–
Analog I/O
113
TPA0+
114
TPBIAS0
Analog I/O
115
V
SSA
—
116
V
DDA
—
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FW32306 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394A | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
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