參數(shù)資料
型號(hào): FW32305
英文描述: 1394A PCI PHY/Link Open Host Controller Interface
中文描述: 1394A端口物理層的PCI /鏈接開(kāi)放主機(jī)控制器接口
文件頁(yè)數(shù): 134/152頁(yè)
文件大小: 1625K
代理商: FW32305
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134
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Internal Registers
(continued)
Isochronous DMA Control
The fields in this register control when the isochronous DMA engines access the PCI bus and how much data
they will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394
packet size, host memory buffer size, FIFO constraints, and the PCI cache line size.
This register is accessible via the PCI bus at offset 0x800.
Table 117. Isochronous DMA Control Registers Description
Bits
15:12
Field
Description
IT Maximum Burst The maximum number of quadlets that will be fetched by the IT unit in
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets.
Defaults to 7 (128 quadlets).
IT Threshold
Along with the amount of data remaining to be fetched from the current
host memory buffer, this field defines the number of quadlets that must
be unused in the IT FIFO before the IT unit will request access to the
PCI bus. In effect, this value defines the minimum burst size that, other
factors permitting, will be used in IT. The threshold is 16 * (n + 1)
quadlets and defaults to 3 (64 quadlets).
IR Maximum Burst The maximum number of quadlets that will be written by the IR unit in
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets.
Defaults to 7 (128 quadlets).
IR Threshold
Along with the space remaining in the current host memory buffer, this
field defines the number of quadlets that must be available in the IR
FIFO before the IR unit will request access to the PCI bus. The
threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets).
11:8
7:4
3:0
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