參數(shù)資料
型號: FPD87310
廠商: National Semiconductor Corporation
英文描述: Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述: 通用接口的XGA小組與區(qū)特別職務(wù)隊⑩(低擺幅差分信號)和FPD時序控制鏈路
文件頁數(shù): 3/28頁
文件大?。?/td> 754K
代理商: FPD87310
AC Electrical Characteristics
FPD-Link INPUT TIMING
V
DD
= 3.3V
±
0.3V, V
SS
= 0.0V (Unless otherwise specified).
Symbol
Parameter
RPLLS
FPD-Link Receiver Phase Lock
Loop Wake-up Time
RSKM
RxIN Skew Margin (Note 4)
Conditions
Min
Typ
Max
Units
10
ms
V
DD
= 3.3V, T
A
= 25C
400
ps
Note 4:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.
This margin takes into account transmitter output skew (TCCS) and the setup and hold time (internal data sampling window) allowing for FPD-Link LVDS cable skew
dependent on type/length of cable, and source clock (FPD-Link Transmitter TxCLK IN) jitter.
RSKM
cable skew (type, length) + source clock jitter (cycle to cycle). The specified RSKM minimum assumes a TPPOSmax limit of 200ps (65MHz). This parameter
is Guaranteed by Design.
DS101077-6
FIGURE 1. FPD87310 Input I
DD
Test Pattern
DS101077-7
SW
TCCS
RSKM
Cable Skew Typically 10 ps - 40 ps per foot.
Setup and Hold Time (internal data sampling window)
Transmitter Output Skew
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
FIGURE 2. FPD87310 (FPD-Link Receiver) Input Skew Margin
F
www.national.com
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