參數(shù)資料
型號(hào)： FPD87310
廠商： National Semiconductor Corporation
英文描述： Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述： 通用接口的XGA小組與區(qū)特別職務(wù)隊(duì)⑩（低擺幅差分信號(hào)）和FPD時(shí)序控制鏈路
文件頁數(shù)： 11/28頁
文件大小： 754K
代理商： FPD87310
Programmable Registers
At power-up, data is read from an external EEPROM. If anything other than 00H is read back on the first EEPROM access (in-
dicating EEPROM not present), the internal default values are used.
Pull-Up must be used on EE_SD pin if external EEPROM is not used.
The following parameters are initialized at power up.
TABLE 1. FPD87310 Programmable Register Definition
Control
Registers
Output Format
Control
(16 bits)
EEPROM
Address
082
H
, 081
H
The CONTROL REGISTER provide more setting information to the
input and output interfaces.
Reserved
Output Data Inversion
“0” - Data inversion is Disabled
“1” - Data inversion is Enabled
Output Data Inversion/Polarity
“0” - Data Inversion when GPO[0] is “0”
“1” - Data inversion when GPO[0] is “1”
Reserved
RSDS output setup/hold time control
Unused Pixels
“00” - no unconnected pixels at beginning of first CD
“01” - 1 unconnected pixels at beginning of first CD
“10” - 2 unconnected pixels at beginning of first CD
“11” - 3 unconnected pixels at beginning of first CD
Reserved
Reserved
Reserved
Frame Rate Control (8 bits only)
“0” - Enable Frame Rate Control
“1” - Disable Frame Rate Control (Truncate LSBs)
8/6 Bits Video
“0” - 6 Bits Video
“1” - 8 Bits Video
Reserved
Black or White data Generation
“00” - No data manipulation is performed
“10” - Data goes to “0” when GPO[9] is “0”
“11” - Data goes to “1” when GPO[9] is “0”
Black data “0” or White data “1” will be output on lines
>
768.
GPO[9] must be programmed to
>
768 lines for data to be output.
# of 65 MHz clocks after the falling edge of HYSYNC until start of video.
[2:0]
[3]
[4]
[7:5]
[11:8]
[13:12]
[15:14]
[1:0]
[2]
[3]
Input Format
Control
(8 bits)
085
H
[4]
[5]
[7:6]
Horizontal
Backporch
(11 bits)
Vertical
Backporch
(11 bits)
087
H
, 086
H
089
H
, 088
H
# of HSYNC from VSYNC falling edge until start of video.
F
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FPD87310VHB 功能描述:IC CTRLR PANEL TIMING 80-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
FPD87346 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs
FPD87346BXA 制造商:TI 制造商全稱:Texas Instruments 功能描述:FPD87346BXA Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs
FPD87346BXAVS 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:
FPD87346BXAVS/NOPB 功能描述:IC TIMING CTLR XGA/WXGA 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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