參數(shù)資料
型號： FPD87310
廠商： National Semiconductor Corporation
英文描述： Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述： 通用接口的XGA小組與區(qū)特別職務(wù)隊(duì)⑩（低擺幅差分信號）和FPD時序控制鏈路
文件頁數(shù)： 23/28頁
文件大小： 754K
代理商： FPD87310
Appendix A: GPO (General
Purpose Output) Programming
Examples
(Continued)
GPO Programming Example #4c:
Generate a control signal which toggles at 20 output clocks
after end of each output line during horizontal blanking and
alternates polarity each frame.
This control signal is used as the reversal signal.
Based on 65 MHz XGA video, 1024 pixel/line,
768 lines/frame.
Horizontal time (clocks/line) = 1300 dot clocks
Vertical period (lines/frame) = 850 lines
Control is active beginning at line
#
1 and remains active for
line
#
769.
(Odd number programmed in Vertical Duration Register
causes control signal to alternate polarity each frame)
GPO Vertical Start Register = 1
(0001
H
)
GPO Vertical Duration Register = 769
(0301
H
)
Positive going pulse causes output to toggle.
Edge occurs 20 output clocks after end of each line (1024 +
20 = 1044). Pulse duration is not critical since the output will
be in toggle mode, but it cannot be “0”.
Note:
4 pixel counts are added to the output data start # because the GPO
pixel count begins 4 clocks prior to the output data. Shown as “Figure
17 Internal Pixel Position Counter.”
GPO
Horizontal
Start
Register
[1044+4=1048]
GPO Horizontal Duration Register = 16
(0010
H
)
The controlled pulses are positive (bit[0] = “0”) and the toggle
circuitry is enabled (bit[1] = “1”).
GPO Control Register = 2
(02
H
) (00000010
B
)
(For a second control signal of opposite polarity, (GPO[y])
program another GPO Control Register with same count val-
ues, signal are negative. (bit[0] = “1”).
GPO Control Register = 3
(03
H
) (00000011
B
)
=
1048
(0418
H
)
DS101077-28
FIGURE 25. Example
#
4c: GPO Vertical Scope View
F
www.national.com
23
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