參數(shù)資料
型號: FPD87310
廠商: National Semiconductor Corporation
英文描述: Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述: 通用接口的XGA小組與區(qū)特別職務(wù)隊(duì)⑩(低擺幅差分信號)和FPD時(shí)序控制鏈路
文件頁數(shù): 21/28頁
文件大?。?/td> 754K
代理商: FPD87310
Appendix A: GPO (General Purpose Output) Programming Examples
(Continued)
GPO Programming Example #4a:
Generate a control signal which transitions high at end of
each line, has a pulse width of 0.5 μs, and remains low dur-
ing the vertical blanking period.
This control signal is used for latch pulse to the Column Driv-
ers.
Based on 65 MHz XGA video, 1024 pixel/line,
768 lines/frame.
Horizontal time (clocks/line) = 1300 dot clocks
Vertical period (lines/frame) = 850 lines
Vertical control is active beginning at line
#
1 and remains ac-
tive for line
#
768.
GPO Vertical Start Register = 1
(0001
H
)
GPO Vertical Duration Register = 768
(0300
H
)
Positive pulse goes high each line at 1024 output clocks af-
ter last pixel are outputted on R, G, B.
Pulse remains high for 32 output clocks (0.5 μs/15.38 ns =
32.5).
Note:
4 pixel counts are added to the output data start # because the GPO
pixel count begins 4 clocks prior to the output data. Shown as Figure
17 “Internal Pixel Position Counter”.
GPO Horizontal Start Register = 1028
(0404
H
)
GPO Horizontal Duration Register = 32
(0020
H
)
The controlled pulses are positive (bit[0] = “0”) and the toggle
circuitry is disabled (bit[1] = “0”).
GPO Control Register = 0
(00
h
) (00000000
B
)
DS101077-24
FIGURE 21. Example
#
4a: GPO Vertical Scope View
DS101077-25
FIGURE 22. Example
#
4a: GPO Horizontal Scope View
F
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21
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