參數(shù)資料
型號: FPD87310
廠商: National Semiconductor Corporation
英文描述: Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述: 通用接口的XGA小組與區(qū)特別職務隊⑩(低擺幅差分信號)和FPD時序控制鏈路
文件頁數(shù): 22/28頁
文件大?。?/td> 754K
代理商: FPD87310
Appendix A: GPO (General
Purpose Output) Programming
Examples
(Continued)
GPO Programming Example #4b:
Generate a control signal which transitions low 20 output
clocks after the beginning of each output line, has a pulse-
width (low) of 12 μs, and goes high during horizontal blank-
ing.
This control signal is used as an output enable for the Row
Drivers.
Based on 65 MHz XGA video, 1024 pixel/line,
768 lines/frame.
Horizontal time (clocks/line) = 1300 dot clocks.
Vertical period (lines/frame) = 850 lines.
Vertical control is active beginning at line
#
2 and remains ac-
tive for line
#
768.
GPO Vertical Start Register = 2
(0002
H
)
GPO Vertical Duration Register = 768
(0300
H
)
Negative pulse goes low each line at 20 output clocks after
first pixel data are outputted on R, G, B. Pulse remains low
for 780 output clocks (12 μs/15.38 ns = 780).
Note:
4 pixel counts are added to the output data start
#
because the GPO
pixel count begins 4 clocks prior to output data. (Shown as “Figure 17
Internal Pixel Position Counter”.
GPO Horizontal Start Register = 24
(0018
H
)
GPO Horizontal Duration Register = 780
(030c
H
)
The controlled pulses are negative (bit[0] = “1”) and the
toggle circuitry is disabled (bit[1] = “0”).
GPO Control Register = 1
(01
H
) (00000001
B
)
DS101077-26
FIGURE 23. Example
#
4b: GPO Vertical Scope View
DS101077-27
FIGURE 24. Example
#
4b: GPO Horizontal Scope View
F
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