- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375872 > FPD87310 (National Semiconductor Corporation) Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link PDF資料下載
參數(shù)資料
| 型號(hào)： | FPD87310 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link |
| 中文描述： | 通用接口的XGA小組與區(qū)特別職務(wù)隊(duì)⑩（低擺幅差分信號(hào)）和FPD時(shí)序控制鏈路 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 754K |
| 代理商： | FPD87310 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Functional Description
(Continued)
Each output has a Control Register (bit [0]) which defines
the GPO polarity (active high or low). Another bit in the
Control Register (bit [1] enables the “toggle” mode. This
mode is useful in REV generation when alternating polar-
ity is required from line to line. Frame to Frame polarity
changes are made by programming an odd
#
in the ver-
tical duration register when in “toggle” mode.
Two of the General Purpose Outputs have additional capa-
bilities.
GPO[0] is capable of performing line inversion on the output
data. Bits [4,3] of the Output Format Control Register pro-
vides control for this function.
GPO[9] controls output blanking and must be used for this
purpose. If output blanking is not desired, this register must
be programmed to always be active.
Black or White Data Generation (all “0” or “1” data) at the end
of each frame is generated when Input Format Control Reg-
ister bits [7,6] is set “10” or “11”. When those bits are set,
Black or White data is output after line
#
768 if GPO[9] is ac-
tive.
SERIAL EEPROM INTERFACE
The Serial EEPROM Interface controls the FPD87310 initial-
ization. If the first byte word read from the EEPROM is not
“00”, the internal default values are used to initialize all pro-
grammable function of the FPD87310.
At power-up, the FPD87310 configures the internal program-
mable registers with data from the EEPROM. After the
FPD87310 is initialized, the EEPROM can be accessed by
the system in which display configuration and manufacturing
information can be obtained. The EEPROM can be pro-
grammed “in system” providing quick evaluation of different
display timing. External access to the EEPROM must be pre-
ceded by pin TEST[2] = “1” in order to interrupt the
FPD87310
download.
Continuous
EEPROM is also selectable by pin TEST[2] = “0”.
The FPD87310 initialization data begins at EEPROM ad-
dress 080
. The first 128 bytes (00
H
–07F
H
) are reserved for
display identification data.
initialization
with
RSDS OUTPUT VOLTAGE CONTROL
The RSDS output voltage swing is controlled through an ex-
ternal load resistor connected to the R
pin. Typical value for
the R
is 13k
for most applications. However, this is de-
pendent on overall LCD module design characteristics such
as trace impedance, termination, etc. The RSDS output volt-
age is inversely related to the R
value. Lower R
values
will increase the RSDS output voltage swing and conse-
quently overall power consumption will also increase. See
.Figure 13
DS101077-4
FIGURE 11. EEPROM Connection
DS101077-5
FIGURE 12. Without EEPROM
DS101077-35
FIGURE 13. R
PI
Connection Diagram
F
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FPD87346 | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
| FPD87346VS | Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
| FPD87352CXA | +3.3V TFT-LCD Timing Controller with Single LVDS Input/Dual RSDS Outputs Including RTC for TFT-LCD Monitors and TV |
| FPD87370AXA | Low EMI Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs |
| FPD87370AXAVS | Low EMI Low Dynamic Power VGA/XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling RSDS Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FPD87310VHB | 功能描述:IC CTRLR PANEL TIMING 80-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| FPD87346 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS⑩) Outputs |
| FPD87346BXA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FPD87346BXA Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs |
| FPD87346BXAVS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| FPD87346BXAVS/NOPB | 功能描述:IC TIMING CTLR XGA/WXGA 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。