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參數(shù)資料
| 型號(hào)： | FPD87310 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link |
| 中文描述： | 通用接口的XGA小組與區(qū)特別職務(wù)隊(duì)⑩（低擺幅差分信號(hào)）和FPD時(shí)序控制鏈路 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 754K |
| 代理商： | FPD87310 |
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Appendix A: GPO (General
Purpose Output) Programming
Examples
(Continued)
nal will be active. Likewise, two programmable registers
(Horizontal Start and Horizontal Duration) control the hori-
zontal component of the control signal. The Horizontal regis-
ter values determine at what pixel count the signal goes ac-
tive and for how many pixel counts the signal stays active
during each line. The Vertical Component enables the signal
for however many lines programmed for and the Horizontal
Component generates pulses within that vertical time period.
Generally the following types of signals are generated:
1.
DC (either “1” or “0”)
2.
A pulse every line.
3.
A pulse once a frame (either in pixels or lines)
4.
Pulsed during active video (pulses are blanked during
vertical blanking period of frame).
Table 3describes the programming requirements for general
types of pulses generated.
The GPO’s also have a “toggle mode”. This provides the ca-
pability to generate a “REVERSAL” signal used in most LCD
applications. Bit[1] of the Central register is set to a “1” to en-
able toggle mode operation. The GPO is programmed so
that a rising edge is produced when the control signal is re-
quired to toggle. This generally occurs once each line. Also,
the # of edges generated per frame is programmed to be an
odd #. This ensures that the control signal will alternate po-
larity from frame to frame.
Examples of GPO programming to produce specific control
signals are included in the following pages.
TABLE 3. GPO Pulse Generation
Type
Vertical
Start
Vertical
Duration
Horizontal
Start
Horizontal
Duration
GPO Output
1
=0
=0
=0
=0
Stuck 0 (When Output Polarity = “0”)
Stuck 1 (When Output Polarity = “1”)
Polarity control is in GPO Control Register bit [0]
Pulse is generated every line beginning at #C
pixel clocks from start of output line
and lasting for #D pixel clocks.
Pulse begins at line #A, pixel #C and continues to line #(A+B),
pixel #C (multi-line pulse)
Pulse generation begins at line #A and continue for #B lines.
Each pulse begins at pixel #C and lasts for #D pixel counts
2
=0
=0
#C
#D
3
#A
#B
#C
=0
4
#A
#B
#C
#D
Note 5:
GPO[0]: provides for the data inverting function enabled by bit[3] of the Output Format Control Register.
GPO[9]: provides programmable output RGB data, Clock and SP blanking function enabled by bit[6] of the Input Format Control Register (RSR[2:0]P/N, RSG[2:0]P/N,
RSB[2:0]P/N, RSCKP/N and SP).
F
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| FPD87346BXA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FPD87346BXA Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controllerwith Reduced Swing Differential Signaling (RSDS) Outputs |
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