參數(shù)資料
型號: FPD87310
廠商: National Semiconductor Corporation
英文描述: Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link
中文描述: 通用接口的XGA小組與區(qū)特別職務(wù)隊⑩(低擺幅差分信號)和FPD時序控制鏈路
文件頁數(shù): 25/28頁
文件大小: 754K
代理商: FPD87310
Appendix A: GPO (General Purpose Output) Programming Examples
(Continued)
TABLE 4. GPO[0] Inverting and GPO[9] Blanking Logical Function
Output Format
Control Register
bit[7]
Output Format
Control Register
bit[4]
x
0
1
x
0
1
x
0
1
GPO[9]=0
GPO[9]=1
bit[6]
bit[3]
0
1
1
0
1
1
0
1
1
GPO[0]=0
-
inv(data)
-
0
1
0
1
0
1
GPO[0]=1
-
-
inv(data)
0
0
1
1
1
0
GPO[0]=0
-
inv(data)
-
-
inv(data)
-
-
inv(data)
-
GPO[0]=1
-
-
inv(data)
-
-
inv(data)
-
-
inv(data)
0
x
1
0
1
1
Legends:
-
inv(data) output data is inverted
0
output data is all “0”
1
output data is all “1”
output data is unchanged
TABLE 5. GPO[9] Blanking for Clock and SP
Output Format
Control Register
bit[7]
0
1
GPO[9]=0
GPO[9]=1
bit[6]
x
x
Output CLK & SP
No Output (“0”)
Output CLK & SP
Output CLK & SP
DS101077-29
FIGURE 26. GPO[0] Inverting and GPO[9] Blanking Method
F
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